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參數(shù)資料
| 型號： | X9251 |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Quad Digitally-Controlled (XDCP) Potentiometer |
| 中文描述： | 四數(shù)字控制（數(shù)字電位器）電位 |
| 文件頁數(shù)： | 5/25頁 |
| 文件大小： | 549K |
| 代理商： | X9251 |
X9251
Characteristics subject to change without notice.
5 of 25
REV 1.3.3 2/10/04
www.xicor.com
PIN DESCRIPTIONS
Bus Interface Pins
S
ERIAL
O
UTPUT
(SO)
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
S
ERIAL
I
NPUT
(SI)
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the device
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
S
ERIAL
C
LOCK
(SCK)
The SCK input is used to clock data into and out of the
X9251.
H
OLD
(HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
D
EVICE
A
DDRESS
(A1–A0)
The address inputs are used to set the two least
significant bits of the slave address. A match in the
slave address serial data stream must be made with
the address input in order to initiate communication
with the X9251. Device pins A1-A0 must be tie to a
logic level which specify the internal address of the
device, see Figures 2, 3, 4, 5 and 6.
C
HIP
S
ELECT
(CS)
When CS is HIGH, the X9251 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device is in the standby
state. CS LOW enables the X9251, placing it in the
active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer. Since
there are 4 potentiometers, there are 4 sets of R
H
and
R
L
such that R
H0
and R
L0
are the terminals of DCP0
and so on.
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical
potentiometer.
potentiometers, there are 4 sets of R
W
such that R
W0
is the terminals of DCP0 and so on.
Since
there
are
4
Supply Pins
S
YSTEM
S
UPPLY
V
OLTAGE
(V
CC
)
AND
S
UPPLY
G
ROUND
(V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin
is the system ground.
Other Pins
N
O
C
ONNECT
No connect pins should be left floating. This pins are
used for Xicor manufacturing and testing purposes.
H
ARDWARE
W
RITE
P
ROTECT
I
NPUT
(WP)
The WP pin when LOW prevents non-volatile writes to
the Data Registers.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X9251TB24 | Quad Digitally-Controlled (XDCP) Potentiometer |
| X9251TB24-2.7 | Quad Digitally-Controlled (XDCP) Potentiometer |
| X9251TB24I | Quad Digitally-Controlled (XDCP) Potentiometer |
| X9251TB24I-2.7 | Quad Digitally-Controlled (XDCP) Potentiometer |
| X9251TS24 | Quad Digitally-Controlled (XDCP) Potentiometer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X9251_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Digitally-Controlled (XDCP⑩) Potentiometer |
| X9251-2.7 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Single Supply/Low Power/256-Tap/SPI Bus |
| X9251TB24 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Quad Digitally-Controlled (XDCP) Potentiometer |
| X9251TB24-2.7 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Quad Digitally-Controlled (XDCP) Potentiometer |
| X9251TB24I | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Quad Digitally-Controlled (XDCP) Potentiometer |
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