參數(shù)資料
型號(hào): X9251TS24I-2.7
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計(jì)
英文描述: Single Supply/Low Power/256-Tap/SPI Bus
中文描述: QUAD 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24
封裝: 0.300 INCH, PLASTIC, SOIC-24
文件頁(yè)數(shù): 4/25頁(yè)
文件大?。?/td> 549K
代理商: X9251TS24I-2.7
X9251
Characteristics subject to change without notice.
4 of 25
REV 1.3.3 2/10/04
www.xicor.com
PIN CONFIGURATION
PIN ASSIGNMENTS
Note 1:
A0–A1 device address pins must be tied to a logic level.
Pin
(SOIC)
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
20
21
22
23
24
6, 19
Pin
(CSP)
E2
F2
F1
D2
E1
C1
B1
C2
A1
A2
B2
B3
A3
A4
C3
B4
C4
E4
D3
F4
F3
E3
D1, D4
Symbol
SO
A0
R
W3
R
H3
R
L3
V
CC
R
L0
R
H0
R
W0
CS
WP
SI
A1
R
L1
R
H1
R
W1
V
SS
R
W2
R
H2
R
L2
SCK
HOLD
NC
Function
Serial Data Output for SPI bus
Device Address for SPI bus. (See Note 1)
Wiper Terminal of DCP3
High Terminal of DCP3
Low Terminal of DCP3
System Supply Voltage
Low Terminal of DCP0
High Terminal of DCP0
Wiper Terminal of DCP0
SPI bus. Chip Select active low input
Hardware Write Protect – active low
Serial Data Input for SPI bus
Device Address for SPI bus. (See Note 1)
Low Terminal of DCP1
High Terminal of DCP1
Wiper Terminal of DCP1
System Ground
Wiper Terminal of DCP2
High Terminal of DCP2
Low Terminal of DCP2
Serial Clock for SPI bus
Device select. Pauses the SPI serial bus.
No Connect
2
3
4
A
B
C
D
E
F
Top View–Bumps Down
R
W0
R
L0
NC
A
0
HOLD
R
L1
V
CC
R
L3
R
W3
SO
SI
R
W1
SCK
R
L2
WP
NC
R
H0
R
H1
R
H3
V
SS
R
W2
CS
A
1
1
CSP
R
H2
SO
A0
R
W3
R
H3
R
L3
NC
V
CC
R
L0
R
H0
R
W0
CS
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
14
HOLD
SCK
R
L2
R
H2
R
W2
NC
V
SS
R
W1
R
H1
R
L1
A1
SOIC/TSSOP
X9251
13
11
12
SI
WP
相關(guān)PDF資料
PDF描述
X9251TS24IZ Single Supply/Low Power/256-Tap/SPI Bus
X9251TS24IZ-2.7 Single Supply/Low Power/256-Tap/SPI Bus
X9251TS24Z Single Supply/Low Power/256-Tap/SPI Bus
X9251TS24Z-2.7 Single Supply/Low Power/256-Tap/SPI Bus
X9251TV24 Single Supply/Low Power/256-Tap/SPI Bus
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