參數(shù)資料
型號: X9251UV24-2.7
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計(jì)
英文描述: SCR Thyristor; Thyristor Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:400V; On State RMS Current, IT(rms):40A; Peak Non Repetitive Surge Current, Itsm:550A; Gate Trigger Current Max, Igt:35mA RoHS Compliant: Yes
中文描述: QUAD 50K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 256 POSITIONS, PDSO24
封裝: 4.40 MM, TSSOP-24
文件頁數(shù): 6/25頁
文件大?。?/td> 549K
代理商: X9251UV24-2.7
X9251
Characteristics subject to change without notice.
6 of 25
REV 1.3.3 2/10/04
www.xicor.com
PRINCIPLES OF OPERATION
The X9251 is an integrated circuit incorporating four
DCPs and their associated registers and counters, and
a serial interface providing direct communication
between a host and the potentiometers.
DCP Description
Each DCP is implemented with a combination of
resistor elements and CMOS switches. The physical
ends of each DCP are equivalent to the fixed terminals
of a mechanical potentiometer (R
H
and R
L
pins). The
RW pin is an intermediate node, equivalent to the
wiper terminal of a mechanical potentiometer.
The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Counter Register
(WCR).
Power Up and Down Recommendations.
There are no restrictions on the power-up or power-
down conditions of V
CC
and the voltages applied to the
potentiometer pins provided that V
CC
is always more
positive than or equal to V
H
, V
L
, and V
W
, i.e., V
CC
V
H
,
V
L
, V
W
. The V
CC
ramp rate specification is always in
effect.
Figure 1. Detailed Potentiometer Block Diagram
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#0
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
(WCR#)
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
8
8
COUNTER
- - -
DECODE
IF WCR = 00[H] then R
W
is closet to R
L
IF WCR = FF[H] then R
W
is closet to R
H
WIPER
#: 0, 1, 2, or 3
One of Four Potentiometers
DR#2
DR#1
DR#3
DCP
CORE
R
W
R
H
R
L
相關(guān)PDF資料
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