參數(shù)資料
型號: X9251UV24IZ-2.7
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: SCR Thyristor; Thyristor Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:600V; On State RMS Current, IT(rms):55A; Peak Non Repetitive Surge Current, Itsm:700A; Gate Trigger Current Max, Igt:35mA RoHS Compliant: Yes
中文描述: QUAD 50K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 256 POSITIONS, PDSO24
封裝: 4.40 MM, ROHS COMPLIANT, TSSOP-24
文件頁數(shù): 1/25頁
文件大?。?/td> 549K
代理商: X9251UV24IZ-2.7
REV 1.3.3 2/10/04
Characteristics subject to change without notice.
1 of 25
www.xicor.com
X9251
Quad Digitally-Controlled (XDCP
TM
) Potentiometer
FEATURES
Four potentiometers in one package
256 resistor taps–0.4% resolution
SPI Serial Interface for write, read, and transfer
operations of the potentiometer
Wiper resistance: 100
4 Non-volatile data registers for each
potentiometer
Non-volatile storage of multiple wiper positions
Standby current < 5μA max
V
CC
: 2.7V to 5.5V Operation
50K
, 100K
versions of total resistance
100 yr. data retention
Single supply version of X9250
Endurance: 100,000 data changes per bit per
register
24-lead SOIC, 24-lead TSSOP, 24-lead CSP
(Chip Scale Package)
Low power CMOS
typical @ V
CC
= 5V
DESCRIPTION
The X9251 integrates four digitally controlled potentio-
meters (XDCP) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometers are imple-
mented with a combination of resistor elements and
CMOS switches. The position of the wipers are
controlled by the user through the SPI bus interface.
Each potentiometer has associated with it a volatile
Wiper Counter Register (WCR) and four non-volatile
Data Registers that can be directly written to and read
by the user. The content of the WCR controls the
position of the wiper. At power-up, the device recalls
the content of the default Data Registers of each DCP
(DR00, DR10, DR20, and DR30) to the corresponding
WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
Single Supply / Low Power / 256-tap / SPI bus
A
PPLICATION
N
OTES
AND
D
EVELOPMENT
S
YSTEM
A V A I L A B L E
AN99 AN115 AN124 AN133 AN134 AN135
FUNCTIONAL DIAGRAM
POWER UP,
INTERFACE
CONTROL
AND
STATUS
V
CC
V
SS
SPI
R
H0
R
L0
DCP0
R
W0
A1
SO
SI
CS
HOLD
SCK
WP
WCR0
DR00
DR01
DR02
DR03
R
H1
R
L1
DCP1
R
W1
WCR1
DR10
DR11
DR12
DR13
R
H2
R
L2
DCP2
R
W2
WCR2
DR20
DR21
DR22
DR23
R
H3
R
L3
DCP3
R
W3
WCR3
DR30
DR31
DR32
DR33
A0
Interface
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