FN8167.2 November 14, 2005 SDA vs SCL Timing WP, A0, A1, and A2 Pin Timing tBUF
參數(shù)資料
型號(hào): X9252YV24IZ-2.7
廠商: Intersil
文件頁(yè)數(shù): 17/20頁(yè)
文件大?。?/td> 0K
描述: IC POT DGTL QUAD 24-TSSOP
標(biāo)準(zhǔn)包裝: 62
系列: XDCP™
接片: 256
電阻(歐姆): 2.8k
電路數(shù): 4
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲(chǔ)器類(lèi)型: 非易失
接口: I²C(芯片選擇,設(shè)備位址,增/減)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1237 (CN2011-ZH PDF)
6
FN8167.2
November 14, 2005
SDA vs SCL Timing
WP, A0, A1, and A2 Pin Timing
tBUF (Note 5) Bus Free Time (Prior to Any Transmission)
1200
ns
tSU:WPA
(Note 5)
A0, A1, A2 and WP Setup Time
600
ns
tHD:WPA
(Note 5)
A0, A1, A2 and WP Hold Time
600
ns
2-Wire Interface timing (s) (Continued)
SYMBOL
PARAMETER
MIN
MAX
UNITS
tSU:STO
tDH
tHIGH
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
SCL
SDA
(Input Timing)
SDA
(Output Timing)
tF
tLOW
tBUF
tAA
tR
tHD:WP
SCL
SDA IN
WP, A0, A1, or A2
tSU:WP
Clk 1
START
STOP
Increment/Decrement Timing
SYMBOL
PARAMETER
MIN
TYP (Note 4)
MAX
UNITS
tCI
CS to SCL Setup
600
ns
tID (Note 5)
SCL HIGH to U/D, DS0 or DS1 change
600
ns
tDI (Note 5)
U/D, DS0 or DS1 to SCL setup
600
ns
tIL
SCL LOW period
2.5
s
tIH
SCL HIGH period
2.5
s
tIC
SCL inactive to CS inactive (Nonvolatile Store Setup Time)
1
s
tCPHS
CS deselect time (STORE)
10
ms
tCPHNS
(Note 5)
CS deselect time (NO STORE)
1
s
tIW (Note 5)
SCL to RW change
100
500
s
tCYC
SCL cycle time
5
s
tR, tF (Note 5) SCL input rise and fall time
500
s
X9252
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