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參數(shù)資料
| 型號： | X9252YV24IZ-2.7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 0K |
| 描述： | IC POT DGTL QUAD 24-TSSOP |
| 標準包裝： | 62 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 2.8k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標準值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（芯片選擇，設備位址，增/減） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1237 (CN2011-ZH PDF) |
13
FN8167.2
November 14, 2005
DCP Addressing for 2-Wire Interface
Once the register number has been selected by a 2-wire
instruction, then the DCP number is determined by the
Address Byte of the following instruction. Note again that this
enables a complete page write of the DRs of all four
potentiometers at once. The register addresses accessible
in the X9252 include:
All other address bits in the Address Byte must be set to “0”
during 2-wire write operations and their value should be
ignored when read.
Byte Write Operation
For any Byte Write operation, the X9252 requires the Slave
Address byte, an Address Byte, and a Data Byte (See Figure
7). After each of them, the X9252 responds with an ACK.
The master then terminates the transfer by generating a
STOP condition. At this time, if the write operation is to a
volatile register (WCR, or SR), the X9252 is ready for the
next read or write operation. If the write operation is to a
nonvolatile register (DR), and the WP pin is high, the X9252
begins the internal write cycle to the nonvolatile memory.
During the internal nonvolatile write cycle, the X9252 does
not respond to any requests from the master. The SDA
output is at high impedance.
The SR bits and WP pin determine the register being
accessed through the 2-wire interface (See Table 2).
As noted before, any write operation to a Data Register
(DR), also transfers the contents of all the data registers in
that row to their corresponding WCR.
For example, to write 3Ahex to the Data Register 1 of DCP2
the following sequence is required:
During the sequence of this example, WP pin must be high,
and A0, A1, and A2 pins must be low. When completed, the
DR21 register and the WCR2 will be set to 3Ah and the other
Data Register in Row 1 will transfer their other contents to
the respective WCR’s.
TABLE 3. 2-WIRE INTERFACE ADDRESS BYTE
ADDRESS (HEX)
CONTENTS
0
DCP 0
1
DCP 1
2
DCP 2
3
DCP 3
4
Not Used
5
Not Used
6
Not Used
7
Status Register
START
Slave Address
0101 0000
ACK
Address Byte
0000 0111
ACK
Data Byte
0000 0011
ACK
note: at this ACK, the WCRs are all updated with their respective DR.
STOP
START
Slave Address
0101 0000
ACK
Address Byte
0000 0010
ACK
Data Byte
0011 1010
ACK
STOP
(Hardware Address = 000,
and a Write command)
(Indicates Status Register
address)
(Data Register 1 and
NVEnable selected)
(Hardware address = 000,
(Access DCP2)
(Write Data Byte 3Ah)
Write command)
S
t
a
r
t
S
t
o
p
Slave
Address
Byte
Data
Byte
A
C
K
Signals from the
Master
Signals from the
Slave
A
C
K
0
11
A
C
K
Write
Signal at SDA
FIGURE 7. BYTE WRITE SEQUENCE
X9252
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相關代理商/技術參數(shù) |
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