參數(shù)資料
型號: X9259
廠商: Intersil Corporation
英文描述: Single Supply/Low Power/256-Tap/2-Wire bus
中文描述: 單電源/低Power/256-Tap/2-Wire巴士
文件頁數(shù): 3/25頁
文件大?。?/td> 400K
代理商: X9259
X9259
Characteristics subject to change without notice.
3 of 25
REV 1.2.3 4/30/02
www.xicor.com
PIN CONFIGURATION
PIN ASSIGNMENTS
Pin
(SOIC/TSSOP)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
20
21
22
23
24
6, 19
1
Note 1:
A0-A3 Device address pins must be tie to a logic level.
Pin
(XBGA)
F2
F1
D2
E1
E2
C1
B1
C2
A1
A2
B2
B3
A3
A4
C3
B4
C4
E4
D3
F4
F3
E3
D1, D4
E2
Symbol
A0
R
W3
R
H3
R
L3
NC1
V
CC
R
L0
R
H0
R
W0
A2
WP
SDA
A1
R
L1
R
H1
R
W1
V
SS
R
W2
R
H2
R
L2
SCL
A3
NC
NC1
Function
Device Address for 2-Wire bus. (See Note 1)
Wiper Terminal for Potentiometer 3.
High Terminal for Potentiometer 3.
Low Terminal for Potentiometer 3.
Must be left unconnected
System Supply Voltage
Low Terminal for Potentiometer 0.
High Terminal for Potentiometer 0.
Wiper Terminal for Potentiometer 0.
Device Address for 2-Wire bus. (See Note 1)
Hardware Write Protect
Serial Data Input/Output for 2-Wire bus.
Device Address for 2-Wire bus. (See Note 1)
Low Terminal for Potentiometer 1.
High Terminal for Potentiometer 1.
Wiper Terminal for Potentiometer 1.
System Ground
WiperTerminal for Potentiometer 2.
High Terminal for Potentiometer 2.
Low Terminal for Potentiometer 2.
Serial Clock for 2-Wire bus.
Device Address for 2-Wire Bus. (See Note 1)
No Connect
Must be left unconnected
NC1
A0
R
W3
R
H3
R
L3
NC
V
CC
R
L0
R
H0
R
W0
A2
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
14
A3
SCL
R
L2
R
H2
R
W2
NC
V
SS
R
W1
R
H1
R
L1
A1
SOIC/TSSOP
X9259
13
11
12
SDA
WP
2
3
4
A
B
C
D
E
F
Top View–Bumps Down
R
W0
R
L0
NC
A
0
A3
R
L1
V
CC
R
L3
R
W3
NC1
SDA
R
W1
SCL
R
L2
WP
NC
R
H0
R
H1
R
H3
V
SS
R
W2
A
2
A
1
1
XBGA
R
H2
相關(guān)PDF資料
PDF描述
X9259TS24IZ-2.7 Single Supply/Low Power/256-Tap/2-Wire bus
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