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參數(shù)資料
| 型號(hào)： | X9271UV14Z-2.7 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 18/22頁(yè) |
| 文件大小： | 0K |
| 描述： | IC XDCP SGL 256TAP 50K 14-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 95 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±300 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | 6 線 SPI（芯片選擇，設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 管件 |
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5
FN8174.3
June 23, 2011
PIN DESCRIPTIONS
Bus Interface Pins
SERIAL OUTPUT (SO)
The Serial Output (SO) is the serial data output pin.
During a read cycle, data is shifted out on this pin.
Data is clocked out by the falling edge of the serial
clock.
SERIAL INPUT (SI)
The Serial Input (SI) is the serial data input pin. All
operational codes, byte addresses, and data to be
written to the potentiometers and potentiometer
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
SERIAL CLOCK (SCK)
The Serial Clock (SCK) input is used to clock data into
and out of the X9271.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is under way, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH at
all times. CMOS level input.
DEVICE ADDRESS (A1 - A0)
The Device Address (A1 - A0) inputs are used to set
the 8-bit slave address. A match in the slave address
serial data stream must be made with the address
input in order to initiate communication with the
X9271.
CHIP SELECT (CS)
When Chip Select (CS) is HIGH, the X9271 is
deselected, the SO pin is at high impedance, and
(unless an internal write cycle is under way) the device
is in standby state. CS LOW enables the X9271,
placing it in the active power mode. It should be noted
that after a power-up, a HIGH to LOW transition on CS
is required prior to the start of any operation.
Potentiometer Pins
RH, RL
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
RW
The wiper pin (RW) is equivalent to the wiper terminal
of a mechanical potentiometer.
Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS)
The System Supply Voltage (VCC) pin is the system
supply voltage. The Supply Ground (VSS) pin is the
system ground.
Other Pins
HARDWARE WRITE PROTECT INPUT (WP)
The Hardware Write Protect Input (WP) pin, when
LOW, prevents nonvolatile writes to the data registers.
NO CONNECT
No Connect pins should be left floating. These pins
are used for Intersil manufacturing and testing
purposes.
X9271
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X9271UV14ZT1 | 功能描述:IC XDCP SGL 256TAP 50K 14-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):2 溫度系數(shù):標(biāo)準(zhǔn)值 35 ppm/°C 存儲(chǔ)器類型:易失 接口:6 線串行（芯片選擇，遞增，增/減） 電源電壓:2.6 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
| X9271UV-2.7 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Single Supply/Low Power/256-Tap/SPI Bus |
| X9271UVI | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Single Digitally-Controlled (XDCP) Potentiometer |
| X9271UVI-2.7 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Single Supply/Low Power/256-Tap/SPI Bus |
| X9271UXXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DIGITAL POTENTIOMETER|CMOS|BGA|PLASTIC |
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