FN8174.3 June 23, 2011 01 0 1 A1 A0 I3 I2 I1 I0 RB RA P0 SCL SI D7 D6 D5 D4 D3 D2 D1 D0 CS 00 ID3 ID2 ID1 ID0 Device ID Internal Instruction Op" />
參數(shù)資料
型號: X9271UV14Z-2.7
廠商: Intersil
文件頁數(shù): 2/22頁
文件大?。?/td> 0K
描述: IC XDCP SGL 256TAP 50K 14-TSSOP
標準包裝: 95
系列: XDCP™
接片: 256
電阻(歐姆): 50k
電路數(shù): 1
溫度系數(shù): 標準值 ±300 ppm/°C
存儲器類型: 非易失
接口: 6 線 SPI(芯片選擇,設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應商設(shè)備封裝: 14-TSSOP
包裝: 管件
10
FN8174.3
June 23, 2011
01
0
1
A1 A0
I3
I2
I1
I0
RB RA
P0
SCL
SI
D7 D6 D5 D4 D3 D2 D1 D0
CS
00
ID3 ID2 ID1 ID0
Device ID
Internal
Instruction
Opcode
Address
Register
Address
Pot/Bank
Address
00
P1
WCR[7:0] valid only when P1 = P0 = 0;
or
Data Register Bit [7:0] for all values of P1 and P0
FIGURE 2. THREE-BYTE INSTRUCTION SEQUENCE (WRITE)
01
0
1
A1 A0
I3
I2
I1 I0
RB RA
P0
SCL
SI
D7 D6 D5 D4 D3 D2 D1 D0
CS
00
ID3 ID2 ID1 ID0
Device ID
Internal
Instruction
Opcode
Address
Register
Address
Pot/Bank
Address
00
P1
WCR[7:0] valid only when P1 = P0 = 0;
S0
X
XX
X
Don’t Care
or
Data Register Bit [7:0] for all values of P1 and P0
FIGURE 3. THREE-BYTE INSTRUCTION SEQUENCE (READ)
ID3 ID2 ID1 ID0
0
A1 A0
I3
I2
I1
RB RA
P0
SCK
SI
CS
010
1
Device ID
Internal
Instruction
Opcode
Address
Register
0
I0
0
P1
Address
Pot/Bank
Address
0
These commands only valid when P1 = P0 = 0
0
FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE
X9271
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