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參數(shù)資料
| 型號： | X9318 |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Digitally Controlled Potentiometer (XDCP)(單DCP,抽頭位置掉電自動保存,高輸出端電壓,可部分替代X9312W) |
| 中文描述： | 數(shù)控電位器（數(shù)字電位器）（單應(yīng)課稅品許可證，抽頭位置掉電自動保存，高輸出端電壓，可部分替代X9312W） |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 269K |
| 代理商： | X9318 |
12 of 22
AN 139
Application Note
www.xicor.com
January, 2001
output) thereby setting the PWM comparator latch. Thus
the 12V feedback loop, via the PWM comparator, main-
tains a constant 12V output by forcing the output current
to an appropriate value such that the output voltage is
held constant. If the inverting PWM comparator input
does not set the PWM comparator latch, the latch will
automatically be set by the falling edge of the next clock
pulse. This limits the switch ON duty cycle to 50%.
Setting the Overcurrent Limit
The maximum output current over current limit is
provided, Figures 6 and 9, by the U301 internal 1V
Zener diode connected to the non-inverting input of the
PWM comparator shown in Figure 9. This Zener limits
the maximum voltage applied to the non-inverting input
and hence the maximum voltage the inverting input can
attain before the switch ON pulse is terminated. Since
the inverting input voltage is proportional to 12V output
current, this mechanism limits the 12V output current.
Typically this current limit has a wide tolerance. The 1V
Zener 10% tolerance plus the tolerance of all the other
components which convert the 12V output current value
to the PWM comparator inverting input voltage result in
a situation where the worst case 12V overcurrent limit
can be uncomfortably high. 1.5X or more of the
maximum 12V output current is not uncommon. This
forces the designer to insure that the Power Mesh
components can handle these stresses along with the
associated component cost. To alleviate this situation, a
X9315 is used to trim out the tolerances associated with
the overcurrent set point. U302, a Xicor X9315 10kOhm
XDCP device is connected to the PWM comparator
inverting input via R309. R309 injects a current into
U301, pin 3 which is dependent on the XDCP wiper
setting. With the wiper set high, the voltage at U301, pin
3 is increased as shown in the Figure 9 in the lower left
dashed waveform.
This has the effect of reducing the 12V overcurrent limit.
With the XDCP wiper set low, the 12V over current limit
is increased. R301 and C304 provide a controlled rate of
rise of U302 Vcc at turn ON. When U301 becomes
active and U301, pin 8 jumps to 5V. It is essential to
control the rate of rise of U203 Vcc at turn ON such that
it complies with the Xicor X9315 data sheet. Resistors
R311, R312 and R313 in Figure 9 hold the XDCP
programming pins to inactive levels. TP301, TP302 and
TP303 are test points to provide access to the XDCP
programming pins. This overcurrent programming
scheme can set the overcurrent trip point to 5% greater
than the rated output current. Once the overcurrent point
is reached, further reducing the power supply output
load resistance will result in the output voltage falling.
There will be the normal slight increase in output current
when this occurs. Referring to the Primary Control
schematic (Fig. 6), the U301 bias voltage across C302
decreases as the output voltage decreases. When the
output voltage has fallen a few volts, the U301 bias
voltage falls to the U301 low line lockout threshold
(approximately 10V) causing U301 to become inactive.
This stops the PWM drive and the 12V output voltage
drops to zero. Automatic restart occurs when C302 is
recharged to 16V by R305 and R306. Upon restart,
normal operation is restored unless the output overload
remains. If the overload remains, the power supply
operates briefly in overcurrent limit mode until C302 is
discharged to 10V causing U301 to once again become
inactive. Restart attempts will continue until 12V output
overload is removed. There is a relationship between the
overcurrent limit point and the input AC line voltage.
The overcurrent limit point increases a bit with
increasing line voltage. In this design the 120Vac
overcurrent trip point occurs at a 12V output current of
10.67A. This varies from 10.36A at 100Vac to 10.84A at
132Vac. The designer can achieve a first order compen-
sation for this variation if so desired by connecting a
high value resistor from U301, pin 3, to Vraw and reset-
ting the values of R1, R308, R307, C306, C308 and
R309 appropriately. The details of this are beyond the
scope of this application note.
Performance Data for the
Reference Design
The performance data for the reference design is tabu-
lated in Figure 10. Note that the converter frequency
was set via the XDCP converter to 109.6 kHz, well
within 0.5% of the target value of 110kHz. The converter
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