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參數(shù)資料
| 型號： | X9318 |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | Digitally Controlled Potentiometer (XDCP)(單DCP,抽頭位置掉電自動保存,高輸出端電壓,可部分替代X9312W) |
| 中文描述： | 數(shù)控電位器（數(shù)字電位器）（單應(yīng)課稅品許可證，抽頭位置掉電自動保存，高輸出端電壓，可部分替代X9312W） |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 269K |
| 代理商： | X9318 |
5 of 22
AN 139
Application Note
www.xicor.com
January, 2001
Referring to the Front End (Fig.3) schematic, F101
provides protection in the event of a failure which draws
excessive AC line current. F101 is chosen to have an
adequate time delay characteristic such that input surge
current will not blow the fuse.
TH101 is a negative temperature coefficient thermistor.
When cold (input power is initially applied), the ther-
mistor resistance is high enough to limit the inrush
current. When hot, after the power supply is running for
a few seconds, the thermistor resistance drops to a low
value to minimize dissipation.
C101 and C102 are across-the-line safety agency rated X
capacitors which function to attenuate differential mode
conducted EMI. R101 and R102 are bleeder resistors to
discharge C101 and C102 quickly in the event the power
supply is unplugged from the AC line thereby exposing
the line cord plug pins. These bleeder resistors reduce a
potential shock hazard.
L102 is a common mode inductor which provides signif-
icant impedance to common mode EMI. Most of the
common mode EMI current which does flow through
L101 is shunted to ground via C103 and C104. These
capacitors are safety agency rated line-to-ground Y
capacitors. Resistor R103 prevents C103/C104 and
parisitic inductance from forming a high Q resonant
circuit which could cause an unwanted peak in the
common mode noise spectrum. L102 also has a leakage
inductance between the two winding which serves as an
impedance for differential mode conducted noise. L101
functions in a similar manner to L102 except it is a much
smaller value and serves to attenuate high frequency
EMI.
MOV101 is a metal oxide varistor which clamps high
voltage power line spikes to reduce the probability of
damage to down stream circuitry. With S101 in the 240V
position, rectifiers CR101-CR104 act as a full wave
bridge. From the positive end of C105 to the negative
end of C107, the capacitor bank is charged to the peak of
the nominal 240Vac input voltage. With S101 in the
120V position CR102 charges C105 and C106 to the
positive peak of the nominal 120Vac input voltage
whereas CR101 charges C107 and C108 to the negative
peak. Thus for either 120Vac or 240Vac operation the
voltage across the capacitor bank is a nominal 320Vdc.
This voltage is unregulated, contains considerable 2X
power line frequency ripple and may have an instanta-
neous value ranging from 200V to a maximum of 373V.
Power Mesh
Refer to Figure 4. The power mesh is a DC-DC
converter which processes nominal 320Vdc power from
the Front End and delivers a regulated 12Vdc at 10A to
the output.
The topology is known as a single switch forward
converter. The switching frequency was chosen to be
110kHz and trimmed accurately by a Xicor digitally
controlled potentiometer in the Primary Control. This
insures that the 4th harmonic of the switching frequency
will always fall below the 450kHz lower frequency limit
of the FCC conducted EMI requirement despite manu-
facturing component tolerances. As low order EMI
component amplitudes roll off at the reciprocal of
harmonic frequency, this feature results in a 20% reduc-
tion in the value of the main EMI inductor, L102, in the
Front End. The switch function is performed by transis-
tors Q1, Q2, Q3 and associated components. The three
transistors are connected in a cascode arrangement.
Q2 and Q3, 900V devices, operate in parallel as the top
element of the cascode. Q2 and Q3 gates are held at a
relatively constant 14Vdc, the primary bias voltage.
Q2 and Q3 source current is switched by Q1. Resistors
R2 and R3 damp any parasitic inductance/gate input
capacitance resonance to avoid gate voltage ringing.
CR2 and CR3 are 17V Zener diodes to limit Q2 and Q3
gate to source voltage to a safe value under dynamic
conditions. L3 is a center tapped inductor which tends to
force Q2 and Q3 currents to be equal during the
switching intervals to balance switching losses between
Q2 and Q3. R7 across L7 serves to damp parasitic
ringing. Q1 is switched OFF and ON, via R4 and CR4,
by the PWM drive from the Primary Control. R4 damps
Q1 gate voltage ringing during turn ON whereas CR4
allows rapid turn OFF. R8 insures Q1 is OFF in the
absence of gate drive. As Q1 must only support the
maximum source voltage of Q2 and Q3, it is a 60V
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