參數(shù)資料
型號: X93254UV14I-3
廠商: Intersil
文件頁數(shù): 4/8頁
文件大?。?/td> 0K
描述: IC DCP DUAL 50K 32TAP 14-TSSOP
標準包裝: 95
系列: XDCP™
接片: 32
電阻(歐姆): 50k
電路數(shù): 2
溫度系數(shù): 標準值 ±35 ppm/°C
存儲器類型: 非易失
接口: 6 線串行(芯片選擇,遞增,增/減)
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 14-TSSOP
包裝: 管件
4
FN8186.1
February 4, 2008
.
Test Circuit #1
Circuit #2 SPICE Macro Model
DC Operating Specifications
Over recommended operating conditions unless otherwise stated.
SYMBOL
PARAMETER
TEST CONDITIONS/NOTES
MIN
(Note 7)
TYP
(Note 4)
MAX
(Note 7)
UNIT
ICC1
VCC Active Current (Increment) per DCP
CS = VIL, U/D = VIL or VIH and
INC = 0.4V @ max. tCY
50
250
A
ICC2
VCC Active Current (Store) (EEPROM
Store) per DCP
CS = VIH, U/D = VIL or VIH and
INC =VIH @ max. tWR
600
A
ISB
Standby Supply Current
CS = VCC - 0.3V, U/D and INC = VSS
or VCC - 0.3V
1A
ILI
CS1 or CS2
VIN = VCC
±1
A
ILI
CS1 or CS2
VCC = 3V, CS = 0
60
100
150
A
ILI
INC1, INC2, U/D1, U/D2 Input Leakage
Current
VIN = VSS to VCC )±1
A
VIH
CS1, CS2, INC1, INC2, U/D1, U/D2 Input
HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VIL
CS1, CS2, INC1, INC2, U/D1, U/D2 Input
HIGH Voltage
-0.5
VCC x 0.1
V
CIN
CS1, CS2, INC1, INC2, U/D1, U/D2 Input
Capacitance
VCC = 3V, VIN = VSS, TA = +25°C,
f = 1MHz (Note 5)
10
pF
Endurance and Data Retention
PARAMETER
MIN
UNIT
Minimum endurance
200,000
Data changes per bit
Data retention
100
Years
VL
TEST POINT
VH/RH
AC Conditions of Test
Input pulse levels
0V to 3V
Input rise and fall times
10ns
Input reference levels
1.5V
CH
CL
10pF
RH
RTOTAL
CW
25pF
RL
AC Operating Specifications
Over recommended operating conditions, unless otherwise stated. CS, INC, U/D, RH and RL are used to
refer to either CS1 or CS2, etc.
SYMBOL
PARAMETER
MIN
(Note 7)
TYP
(Note 4)
MAX
(Note 7)
UNIT
tCl
CS to INC Setup
100
ns
tlD
INC HIGH to U/D Change
100
ns
tDI
U/D to INC Setup
100
ns
tlL
INC LOW Period
1
s
tlH
INC HIGH Period
1
s
tlC
INC Inactive to CS Inactive
1
s
tCPH
CS Deselect time (No Store)
250
ns
tCPH
CS Deselect time (Store)
10
ms
X93254
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