參數(shù)資料
型號: X9448YS24
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Mixed Signal with 2-Wire Interface
中文描述: 2.5K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24
封裝: PLASTIC, SOIC-24
文件頁數(shù): 7/20頁
文件大?。?/td> 127K
代理商: X9448YS24
X9448
Characteristics subject to change without notice.
7 of 20
REV 1.0 6/21/00
www.xicor.com
Write Data Register (DR)
Write new value to the Register pointed to by P
1
-P
0
and R
1
-R
0
.
Transfer Data Register to Wiper Counter Register or Analog Control Register
Transfer the contents of the Register pointed to by R
1
-R
0
to the WCR or ACR pointed to by P
1
-P
0
.
Transfer Wiper Counter or Analog Control Register to Data Register
Transfer the contents of the WCR or ACR pointed to by P
1
-P
0
to the Register pointed to by R
1
-R
0
.
Global Transfer Data Register to Wiper Counter or Analog Control Register
Transfer the contents of all four Data Registers pointed to by R
1
-R
0
to their respective WCR or ACR.
Global Transfer Wiper Counter or Analog Control Register to Data Register
Transfer the contents of all WCRs and ACRs to their respective data Registers pointed to by R
1
-R
0
.
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
WCR/ACR/DR
addresses
S
A
C
K
register data
(sent by master on SDA)
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0 1 0 1
A
3
A
2
A
1
A
0
1 1 0 0
R
1
R
0
P
1
P
0
0 0
D
5
D
4
D
3
D
2
D
1
D
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
WCR/ACR/DR
addresses
S
A
C
K
S
T
O
P
0
1
0
1
A
3
A
2
A
1
A
0
1
1
0
1
R
1
R
0
P
1
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
WCR/ACR/DR
addresses
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
A
3
A
2
A
1
A
0
1
1
1
0
R
1
R
0
P
1
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
DR
addresses
S
A
C
K
S
T
O
P
0
1
0
1
A
3
A
2
A
1
A
0
0
0
0
1
R
1
R
0
0
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
DR
addresses
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
A
3
A
2
A
1
A
0
1
0
0
0
R
1
R
0
0
0
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