參數(shù)資料
型號(hào)： X9520
廠商： Intersil Corporation
英文描述： Triple DCP, POR,2kbit EEPROM Memory, Dual Voltage Monitors
中文描述： 三氯酚，葡萄牙，2kbit EEPROM存儲(chǔ)器，雙電壓監(jiān)視器
文件頁(yè)數(shù)： 11/33頁(yè)
文件大?。?/td> 561K
代理商： X9520
11
FN8206.0
March 8, 2005
EEPROM Array Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of the
Slave Address Byte is set to one. There are three basic
read operations: Current EEPROM Address Read, Ran-
dom EEPROM Read, and Sequential EEPROM Read.
Current EEPROM Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented
by one. Therefore, if the last read was to address n, the
next read operation would access data from address
n+1. On power-up, the address of the address counter is
undefined, requiring a read or write operation for initial-
ization.
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an ACKNOWLEDGE and
then transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond
with an ACKNOWLEDGE during the ninth clock and then
issues a STOP condition (See Figure 14 for the address,
ACKNOWLEDGE, and data transfer sequence).
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read oper-
ation, the master must either issue a STOP condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a STOP condition.
Another important point to note regarding the “Current
EEPROM Address Read” , is that this operation is not
available if the last executed operation was an access to
a DCP or the CONSTAT Register (i.e.: an operation
using the Device Type Identifier 1010111 or 1010010).
Immediately after an operation to a DCP or CONSTAT
Register is performed, only a “Random EEPROM Read”
is available. Immediately following a “Random EEPROM
Read” , a “Current EEPROM Address Read” or “Sequen-
tial EEPROM Read” is once again available (assuming
that no access to a DCP or CONSTAT Register occur in
the interim).
Random EEPROM Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master
must first perform a “dummy” write operation. The master
issues the START condition and the Slave Address Byte,
receives an ACKNOWLEDGE, then issues an Address
address
15
address
11
5 bytes
7 bytes
address
= 6
address pointer
ends here
Addr = 7
Figure 13. Example: Writing 12 bytes to a 16-byte page starting at location 11.
10
10
10
10
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Figure 14. Current EEPROM Address Read Sequence
1
01 0
0 0 0
X9520
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