參數(shù)資料
型號: X9520V20IB
廠商: Intersil Corporation
英文描述: Triple DCP, POR,2kbit EEPROM Memory, Dual Voltage Monitors
中文描述: 三氯酚,葡萄牙,2kbit EEPROM存儲器,雙電壓監(jiān)視器
文件頁數(shù): 5/33頁
文件大?。?/td> 561K
代理商: X9520V20IB
5
FN8206.0
March 8, 2005
minate further data transmissions if an ACKNOWLEDGE
is not detected. The master must then issue a STOP
condition to place the device into a known state.
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the X9520
can be split up into three main parts:
—Three Digitally Controlled Potentiometers (DCPs)
—EEPROM array
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on each
of these individual parts, a 1, 2 or 3 Byte protocol is used.
All operations however must begin with the Slave
Address Byte being issued on the SDA pin. The Slave
address selects the part of the X9520 to be addressed,
and specifies if a Read or Write operation is to be per-
formed.
It should be noted that in order to perform a write opera-
tion to either a DCP or the EEPROM array, the Write
Enable Latch (WEL) bit must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 13.)
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of three parts:
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9520.
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 000 internally
selects the EEPROM array, while setting these bits to
111 selects the DCP structures in the X9520. The
CONSTAT Register may be selected using the Inter-
nal Device Address 010.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
Data Output
from
Transmitter
Data Output
from
Receiver
8
1
9
Start
Acknowledge
Figure 3.
Acknowledge Response From Receiver
SCL
from
Master
SA6
SA7
SA5
SA3
SA2
SA1
SA0
DEVICE TYPE
IDENTIFIER
READ /
WRITE
SA4
Internal Address
(SA3 - SA1)
000
010
111
Internally Addressed
Device
EEPROM Array
CONSTAT Register
DCP
Bit SA0
0
1
Operation
WRITE
READ
R/W
Figure 4.
Slave Address Format
1
0
1
0
ADDRESS
INTERNAL
DEVICE
X9520
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