參數(shù)資料
型號(hào): X96010
廠商: Intersil Corporation
英文描述: Sensor Conditioner with Dual Look Up Table Memory and DACs(傳感器調(diào)節(jié)器,帶雙查找表存儲(chǔ)器及DACs)
中文描述: 傳感器護(hù)發(fā)高達(dá)表內(nèi)存和DAC(傳感器調(diào)節(jié)器,帶雙查找表存儲(chǔ)器及DAC的雙查找)
文件頁(yè)數(shù): 11/26頁(yè)
文件大?。?/td> 372K
代理商: X96010
11
FN8214.1
October 25, 2005
Figure 4. Control and Status Register Format
Byte
MSB
LSB
80h
Register
Name
Control 0
0
0
I1DS
NV1234
I2DS
ADCfiltOff
1
VRM
Non-Volatile
81h
Control 1
Volatile or
Non-Volatile
Reserved
Reserved
L1DA5
L1DA4
L1DA3
L1DA2
L1DA1
L1DA0
82h
Control 2
Volatile or
Non-Volatile
Reserved
Reserved
L2DA5
L2DA4
L2DA3
L2DA2
L2DA1
L2DA0
83h
Control 3
Volatile or
Non-Volatile
D1DA7
D1DA6
D1DA5
D1DA4
D1DA3
D1DA2
D1DA1
D1DA0
84h
Control 4
Volatile or
Non-Volatile
D2DA7
D2DA6
D2DA5
D2DA4
D2DA3
D2DA2
D2DA1
D2DA0
85h
Control 5
Non-Volatile
D2DAS
L2DAS
D1DAS
L1DAS
0
0
0
0
86h
Control 6
Volatile
WEL
Reserved
Reserved Reserved
Reserved
Reserved
Reserved
Reserved
87h
Status
Volatile
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
7
6
5
4
3
2
1
0
Address
Registers in byte addresses 88h through 8Fh are reserved.
Register bits shown as 0 or 1 should always use those values for proper operation.
Direct Access to LUT1
Direct Access to LUT2
Direct Access to DAC1
Direct Access to DAC2
ADC Output
I1 and I2 Direction
0: Source
1: Sink
Control
1, 2, 3, 4
Volatility
0: Volatile
1: Non-
volatile
Voltage
Reference
Mode
0: Internal
1: External
Direct
Access
to DAC2
0: Disabled
1: Enabled
Direct
Access
to LUT2
0: Disabled
1: Enabled
Direct
Access
to DAC1
0: Disabled to LUT1
1: Enabled
Direct
Access
1: Enabled
Write
Enable
Latch
0: Write
Disabled
1: Write
Enabled
ADC
filtering
0: On
1: Off
X96010
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