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參數(shù)資料
| 型號： | X96010 |
| 廠商： | Intersil Corporation |
| 英文描述： | Sensor Conditioner with Dual Look Up Table Memory and DACs(傳感器調(diào)節(jié)器，帶雙查找表存儲器及DACs) |
| 中文描述： | 傳感器護發(fā)高達表內(nèi)存和DAC（傳感器調(diào)節(jié)器，帶雙查找表存儲器及DAC的雙查找） |
| 文件頁數(shù)： | 23/26頁 |
| 文件大?。?/td> | 372K |
| 代理商： | X96010 |
23
FN8214.1
October 25, 2005
Page Write Operation
The 144-byte memory array is physically realized as
one contiguous array, organized as 9 pages of 16
bytes each. “Page Write” operations can be performed
to any of the LUT pages. In order to perform a Page
Write operation the Write Enable Latch (WEL) bit in
Control register 6 must first be set (See “WEL: Write
Enable Latch (Volatile)” on page 13.)
A Page Write operation is initiated in the same manner
as the byte write operation; but instead of terminating
the write cycle after the first data byte is transferred,
the master can transmit up to 16 bytes (See Figure
18). After the receipt of each byte, the X96010
responds with an ACK, and the internal byte address
counter is incremented by one. The page address
remains constant. When the counter reaches the end
of the page, it “rolls over” and goes back to the first
byte of the same page.
For example, if the master writes 12 bytes to a 16-byte
page starting at location 11 (decimal), the first 5 bytes
are written to locations 11 through 15, while the last 7
bytes are written to locations 0 through 6 within that
page. Afterwards, the address counter would point to
location 7. If the master supplies more than 16 bytes of
data, then new data overwrites the previous data, one
byte at a time (See Figure 19).
The master terminates the loading of Data Bytes by
issuing a STOP condition, which initiates the nonvola-
tile write cycle. As with the Byte Write operation, all
inputs are disabled until completion of the internal
write cycle.
A Page Write operation cannot be performed on the
page at locations 80h through 8Fh. Next section
describes the special cases within that page.
A Page Write operation starting with byte address
FFh, accesses the page between locations 100h and
10Fh. The first data byte of such operation is written to
location 100h.
Writing to Control Registers
The bytes at location 80h, 85h and 86h are written
using Byte Write operations. They cannot be written
using a Page Write operation.
Control bytes 1 through 4, at locations 81h through 84h
respectively, are written during a single operation (See
Figure 20). The sequence must be: a START, followed
by a Slave Address byte, with the R/W bit equal to “0”,
followed by 81h as the Address Byte, and then followed
by exactly four Data Bytes, and a STOP condition. The
first data byte is written to location 81h, the second to
82h, the third to 83h, and the last one to 84h.
S
t
a
r
t
S
t
o
p
Slave
Address
Address
Byte
Data
Byte
A
C
K
Signals from
the Master
Signals from
the Slave
A
C
K
1
0
1
0
0
A
C
K
Write
Signal at SDA
Figure 17. Byte Write Sequence
2 < n < 16
Signals from
the Master
Signals from
the Slave
Signal at SDA
S
t
a
r
t
Slave
Address
Address
Byte
A
C
K
A
C
K
1
0
1
0
0
Data Byte (1)
S
t
o
p
A
C
K
A
C
K
Data Byte (n)
Write
Figure 18. Page Write Operation
X96010
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