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參數(shù)資料
| 型號： | XA-G39 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | XA 16-bit microcontroller family XA 16-bit microcontroller 32K FLASH/1K RAM, watchdog, 2 UARTs |
| 中文描述： | 的XA 16位微控制器系列的XA 16位微控制器32K的FLASH/1K內(nèi)存，看門狗，2個(gè)UART |
| 文件頁數(shù)： | 33/42頁 |
| 文件大小： | 217K |
| 代理商： | XA-G39 |
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Philips Semiconductors
Preliminary data
XA-G39
XA 16-bit microcontroller family
32K Flash/1K RAM, watchdog, 2 UARTs
2002 Mar 13
33
AC ELECTRICAL CHARACTERISTICS (5 V)
V
DD
= 4.5 V to 5.5 V; T
amb
= 0 to +70
°
C for commercial; V
DD
= 4.75 V to 5.25 V, –40
°
C to +85
°
C for industrial.
SYMBOL
FIGURE
PARAMETER
VARIABLE CLOCK
UNIT
MIN
MAX
External Clock
f
C
t
C
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Address Cycle
t
CRAR
t
LHLL
t
AVLL
t
LLAX
Code Read Cycle
t
PLPH
t
LLPL
t
AVIVA
t
AVIVB
t
PLIV
t
PXIX
t
PXIZ
t
IXUA
Data Read Cycle
t
RLRH
t
LLRL
t
AVDVA
t
AVDVB
t
RLDV
t
RHDX
t
RHDZ
t
DXUA
Data Write Cycle
t
WLWH
t
LLWL
t
QVWX
t
WHQX
t
AVWL
t
UAWH
Wait Input
t
WTH
t
WTL
NOTES:
1. Load capacitance for all outputs = 80pF.
2. Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers (BTRH and BTRL).
Refer to the XA User Guidefor details of the bus timing settings.
V1)
This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL register.
V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1.
Oscillator frequency
Clock period and CPU timing cycle
Clock high time
Clock low time
Clock rise time
Clock fall time
0
30
MHz
ns
ns
ns
ns
ns
26
26
26
26
26
1/f
C
t
C
* 0.5
7
t
C
* 0.4
7
5
5
25
20
20
20
Delay from clock rising edge to ALE rising edge
ALE pulse width (programmable)
Address valid to ALE de-asserted (set-up)
Address hold after ALE de-asserted
5
46
ns
ns
ns
ns
(V1 * t
C
) – 6
(V1 * t
C
) – 14
(t
C
/2) – 10
20
20
20
21
20
20
20
20
PSEN pulse width
ALE de-asserted to PSEN asserted
Address valid to instruction valid, ALE cycle (access time)
Address valid to instruction valid, non-ALE cycle (access time)
PSEN asserted to instruction valid (enable time)
Instruction hold after PSEN de-asserted
Bus 3-State after PSEN de-asserted (disable time)
Hold time of unlatched part of address after instruction latched
(V2 * t
C
) – 10
(t
C
/2) – 7
ns
ns
ns
ns
ns
ns
ns
ns
(V3 * t
C
) – 36
(V4 * t
C
) – 29
(V2 * t
C
) – 29
0
t
C
– 8
0
22
22
22
23
22
22
22
22
RD pulse width
ALE de-asserted to RD asserted
Address valid to data input valid, ALE cycle (access time)
Address valid to data input valid, non-ALE cycle (access time)
RD low to valid data in, enable time
Data hold time after RD de-asserted
Bus 3-State after RD de-asserted (disable time)
Hold time of unlatched part of address after data latched
(V7 * t
C
) – 10
(t
C
/2) – 7
ns
ns
ns
ns
ns
ns
ns
ns
(V6 * t
C
) – 36
(V5 * t
C
) – 29
(V7 * t
C
) – 29
0
t
C
– 8
0
24
24
24
24
24
24
WR pulse width
ALE falling edge to WR asserted
Data valid before WR asserted (data setup time)
Data hold time after WR de-asserted (Note 6)
Address valid to WR asserted (address setup time) (Note 5)
Hold time of unlatched part of address after WR is de-asserted
(V8 * t
C
) – 10
(V12 * t
C
) – 10
(V13 * t
C
) – 22
(V11 * t
C
) – 7
(V9 * t
C
) – 22
(V11 * t
C
) – 7
ns
ns
ns
ns
ns
ns
25
25
WAIT stable after bus strobe (RD, WR, or PSEN) asserted
WAIT hold after bus strobe (RD, WR, or PSEN) assertion
(V10 * t
C
) – 30
ns
ns
(V10 * t
C
) – 5
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