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參數資料
| 型號： | XA2C384-10TQG144I |
| 廠商： | Xilinx Inc |
| 文件頁數： | 1/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 384MCELL 118 I/O 144TQFP |
| 產品培訓模塊： | CoolRunner-II CPLD Starter Kit |
| 標準包裝： | 60 |
| 系列： | CoolRunner II |
| 可編程類型： | 系統內可編程 |
| 最大延遲時間 tpd(1)： | 9.2ns |
| 電壓電源 - 內部： | 1.7 V ~ 1.9 V |
| 邏輯元件/邏輯塊數目： | 24 |
| 宏單元數： | 384 |
| 門數： | 9000 |
| 輸入/輸出數： | 118 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
DS556 (v1.1) May 5, 2007
1
Product Specification
2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
AEC-Q100 device qualification and full PPAP support
available in both I-grade and extended temperature
Q-grade
Guaranteed to meet full electrical specifications over
TA = -40° C to +105° C with TJ Maximum = +125° C
(Q-grade)
Optimized for 1.8V systems
Industry’s best 0.18 micron CMOS CPLD
-
Optimized architecture for effective logic synthesis
-
Multi-voltage I/O operation — 1.5V to 3.3V
Available in the following package option
-
144-pin TQFP with 118 user I/O
-
Pb-free only for this package
Advanced system features
-
Fastest in system programming
1.8V ISP using IEEE 1532 (JTAG) interface
-
IEEE1149.1 JTAG Boundary Scan Test
-
Optional Schmitt-trigger input (per pin)
-
Unsurpassed low power management
DataGATE enable (DGE) signal control
-
Four separate I/O banks
-
RealDigital 100% CMOS product term generation
-
Flexible clocking modes
Optional DualEDGE triggered registers
Clock divider (divide by 2,4,6,8,10,12,14,16)
CoolCLOCK
-
Global signal options with macrocell control
Multiple global clocks with phase selection per
macrocell
Multiple global output enables
Global set/reset
-
Advanced design security
-
PLA architecture
Superior pinout retention
100% product term routability across function
block
-
Open-drain output option for Wired-OR and LED
drive
-
Optional bus-hold, 3-state or weak pullup on
selected I/O pins
-
Optional configurable grounds on unused I/Os
-
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
-
Hot pluggable
Refer to the CoolRunner-II Automotive CPLD family data
sheet for architecture description.
WARNING: Programming temperature range of
TA = 0° C to +70° C.
Description
The CoolRunner-II Automotive 384-macrocell device is
designed for both high performance and low power applica-
tions. This lends power savings to high-end communication
equipment and high speed to battery operated devices. Due
to the low power stand-by and dynamic operation, overall
system reliability is improved
This device consists of twenty four Function Blocks
inter-connected by a low power Advanced Interconnect
Matrix (AIM). The AIM feeds 40 true and complement inputs
to each Function Block. The Function Blocks consist of a 40
by 56 P-term PLA and 16 macrocells which contain numer-
ous configuration bits that allow for combinational or regis-
tered modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt-trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as direct input registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
Circuitry has also been included to divide one externally
supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.
The use of the clock divide (division by 2) and DualEDGE
flip-flop gives the resultant CoolCLOCK feature.
0
XA2C384 CoolRunner-II
Automotive CPLD
DS556 (v1.1) May 5, 2007
00
Product Specification
R
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