參數(shù)資料
型號(hào)： XA3S1400A-4FGG484Q
廠商： Xilinx Inc
文件頁(yè)數(shù)： 12/57頁(yè)
文件大小： 0K
描述： IC FPGA SPARTAN3A 1400K 484-FBGA
標(biāo)準(zhǔn)包裝： 1
系列： Spartan®-3A XA
LAB/CLB數(shù)： 2816
邏輯元件/單元數(shù)： 25344
RAM 位總計(jì)： 589824
輸入/輸出數(shù)： 375
門(mén)數(shù)： 1400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 125°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FBGA
XA Spartan-3A Automotive FPGA Family Data Sheet
DS681 (v2.0) April 22, 2011
Product Specification
2
Key Feature Differences from Commercial XC Devices
AEC-Q100 device qualification and full production part approval process (PPAP) documentation support available in
both extended temperature I- and Q-Grades
Guaranteed to meet full electrical specification over the TJ = –40°C to +125°C temperature range (Q-Grade)
XA Spartan-3A devices are available in the -4 speed grade only
PCI-66 is not supported in the XA Spartan-3A FPGA product line
Platform Flash is not supported within the XA family
XA Spartan-3A devices are available in Pb-Free packaging only.
MultiBoot is not supported in XA versions of this product.
The XA Spartan-3A device must be power cycled prior to reconfiguration.
Architectural Overview
The XA Spartan-3A family architecture consists of five fundamental programmable functional elements:
Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage
elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data.
Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. IOBs
support bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including several
high-performance differential standards. Double Data-Rate (DDR) registers are included.
Block RAM provides data storage in the form of 18-Kb dual-port blocks.
Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product.
Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying,
multiplying, dividing, and phase-shifting clock signals.These elements are organized as shown in Figure 1. A dual ring
of staggered IOBs surrounds a regular array of CLBs. Each device has two columns of block RAM. Each RAM column
consists of several 18-Kb RAM blocks. Each block RAM is associated with a dedicated multiplier. The DCMs are
positioned in the center with two at the top and two at the bottom of the device. The XA3S700A and XA3S1400A add
two DCMs in the middle of the two columns of block RAM and multipliers. The XA Spartan-3A family features a rich
network of routing that interconnect all five functional elements, transmitting signals among them. Each functional
element has an associated switch matrix that permits multiple connections to the routing.
Table 1: Summary of XA Spartan-3A FPGA Attributes)
Device
System
Gates
Equivalent
Logic
Cells
CLB Array
(One CLB = Four Slices)
Distributed
RAM bits(1)
Block
RAM
bits(1)
Dedicated
Multipliers
DCMs
Maximum
User I/O
Maximum
Differential
I/O Pairs
Rows Columns
Total
CLBs
Total
Slices
XA3S200A
200K
4,032
32
16
448
1,792
28K
288K
16
4
195
90
XA3S400A
400K
8,064
40
24
896
3,584
56K
360K
20
4
311
142
XA3S700A
700K
13,248
48
32
1,472
5,888
92K
360K
20
8
372
165
XA3S1400A 1400K
25,344
72
40
2,816 11,264
176K
576K
32
8
375
165
Notes:
1.
By convention, one Kb is equivalent to 1,024 bits.
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