參數(shù)資料
型號(hào)： XA3S1400A-4FGG484Q
廠商： Xilinx Inc
文件頁(yè)數(shù)： 9/57頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SPARTAN3A 1400K 484-FBGA
標(biāo)準(zhǔn)包裝： 1
系列： Spartan®-3A XA
LAB/CLB數(shù)： 2816
邏輯元件/單元數(shù)： 25344
RAM 位總計(jì)： 589824
輸入/輸出數(shù)： 375
門數(shù)： 1400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 125°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FBGA
XA Spartan-3A Automotive FPGA Family Data Sheet
DS681 (v2.0) April 22, 2011
Product Specification
17
Device DNA Data Retention, Read Endurance
Switching Characteristics
All XA Spartan-3A FPGAs ship in the -4 speed grade. Switching characteristics in this document are designated as
Production as shown in Table 16.
Production: These specifications are approved once enough production silicon of a particular device family member has
been characterized to provide full correlation between speed files and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal notification of any subsequent changes.
Software Version Requirements
Production-quality systems must use FPGA designs compiled using a speed file designated as PRODUCTION status.
FPGA designs using a less mature speed file designation should only be used during system prototyping or pre-production
qualification. FPGA designs with speed files designated as Preview, Advance, or Preliminary should not be used in a
production-quality system.
Whenever a speed file designation changes, as a device matures toward Production status, rerun the latest Xilinx ISE
software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software
updates.
All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise
noted, the published parameter values apply to all XA Spartan-3A devices, and AC and DC characteristics are specified
using the same numbers for both I-Grade and Q-Grade.
To create a Xilinx user account and sign up for automatic E-mail notification whenever this data sheet is updated:
Timing parameters and their representative values are selected for inclusion below either because they are important as
general design requirements or they indicate fundamental device performance characteristics. The XA Spartan-3A FPGA
speed files (v1.41), part of the Xilinx Development Software, are the original source for many but not all of the values. The
speed grade designations for these files are shown in Table 16. For more complete, more precise, and worst-case data, use
the values reported by the Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to
the simulation netlist.
Table 17 provides the recent history of the XA Spartan-3A FPGA speed files.
Table 15: Device DNA Identifier Memory Characteristics
Symbol
Description
Minimum
Units
DNA_CYCLES
Number of READ operations or JTAG ISC_DNA read operations. Unaffected by
HOLD or SHIFT operations.
30,000,000
Read
cycles
Table 16: XA Spartan-3A FPGA v1.41 Speed Grade Designations
Device
Production
XA3S200A
-4
XA3S400A
-4
XA3S700A
-4
XA3S1400A
-4
Table 17: XA Spartan-3A FPGA Speed File Version History
Version
ISE Release
Description
1.39
10.1.01i
Initial release.
1.40
10.1.02i
Updated input timing adjustments.
1.41
10.1.03i
Updated output timing adjustments.
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