參數(shù)資料
型號: XA3S500E-4CPG132Q
廠商: Xilinx Inc
文件頁數(shù): 6/37頁
文件大小: 0K
描述: IC FPGA SPARTAN-3E 500K 132CSBGA
標(biāo)準(zhǔn)包裝: 360
系列: Spartan®-3E XA
LAB/CLB數(shù): 1164
邏輯元件/單元數(shù): 10476
RAM 位總計: 368640
輸入/輸出數(shù): 92
門數(shù): 500000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 125°C
封裝/外殼: 132-TFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 132-CSPBGA(8x8)
DS635 (v2.0) September 9, 2009
Product Specification
14
R
Switching Characteristics
I/O Timing
Figure 5: External Termination Resistors for BLVDS Transmitter and BLVDS Receiver
Z0 = 50
Ω
Z0 = 50
Ω
140
Ω
165
Ω
165
Ω
100
Ω
DS635_05_082807
VCCO = 2.5V
1/4th of Bourns
Part Number
CAT16-LV4F12
VCCO = 2.5V
1/4th of Bourns
Part Number
CAT16-PT4F4
Table 13: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Symbol
Description
Conditions
Device
-4 Speed
Grade
Units
Max
Clock-to-Output Times
TICKOFDCM
When reading from the Output
Flip-Flop (OFF), the time from
the active transition on the
Global Clock pin to data
appearing at the Output pin. The
DCM is used.
LVCMOS25(2), 12mA
output drive, Fast slew rate,
with DCM(3)
XA3S100E
2.79
ns
XA3S250E
3.45
ns
XA3S500E
3.46
ns
XA3S1200E
3.46
ns
XA3S1600E
3.45
ns
TICKOF
When reading from OFF, the
time from the active transition on
the Global Clock pin to data
appearing at the Output pin. The
DCM is not used.
LVCMOS25(2), 12mA
output drive, Fast slew rate,
without DCM
XA3S100E
5.92
ns
XA3S250E
5.43
ns
XA3S500E
5.51
ns
XA3S1200E
5.94
ns
XA3S1600E
6.05
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in
2.
This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 17. If the latter is true, add the appropriate Output adjustment from Table 18.
3.
DCM output jitter is included in all measurements.
4.
For minimums, use the values reported by the Xilinx timing analyzer.
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