XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
18
I/O Timing
Pin-to-Pin Clock-to-Output Times
Pin-to-Pin Setup and Hold Times
Table 18: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Symbol
Description
Conditions
Device
Speed Grade: -4
Units
Max
Clock-to-Output Times
TICKOFDCM
When reading from the Output Flip-Flop (OFF),
the time from the active transition on the Global
Clock pin to data appearing at the Output pin.
The DCM is in use.
output drive, Fast slew
XA3SD1800A
3.51
ns
XA3SD3400A
3.82
ns
TICKOF
When reading from OFF, the time from the
active transition on the Global Clock pin to data
appearing at the Output pin. The DCM is not in
use.
output drive, Fast slew
rate, without DCM
XA3SD1800A
5.58
ns
XA3SD3400A
6.13
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in
Table 27 and are based on the operating conditions set forth in
2.
This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from
Table 23. If the latter is true, add the appropriate Output adjustment from
Table 26.
3.
DCM output jitter is included in all measurements.
Table 19: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Symbol
Description
Conditions
Device
Speed Grade: -4
Units
Min
Setup Times
TPSDCM
When writing to the Input Flip-Flop (IFF), the
time from the setup of data at the Input pin to
the active transition at a Global Clock pin. The
DCM is in use. No Input Delay is programmed.
IFD_DELAY_VALUE = 0,
XA3SD1800A
3.11
ns
XA3SD3400A
2.49
ns
TPSFD
When writing to IFF, the time from the setup of
data at the Input pin to an active transition at
the Global Clock pin. The DCM is not in use.
The Input Delay is programmed.
IFD_DELAY_VALUE = 6,
without DCM
XA3SD1800A
3.39
ns
XA3SD3400A
3.08
ns
Hold Times
TPHDCM
When writing to IFF, the time from the active
transition at the Global Clock pin to the point
when data must be held at the Input pin. The
DCM is in use. No Input Delay is programmed.
IFD_DELAY_VALUE = 0,
XA3SD1800A
–0.38
ns
XA3SD3400A
–0.26
ns
TPHFD
When writing to IFF, the time from the active
transition at the Global Clock pin to the point
when data must be held at the Input pin. The
DCM is not in use. The Input Delay is
programmed.
IFD_DELAY_VALUE = 6,
without DCM
XA3SD1800A
–0.71
ns
XA3SD3400A
–0.65
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in
Table 27 and are based on the operating conditions set forth in
2.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from
Table 23. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from
Table 23. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
4.
DCM output jitter is included in all measurements.