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參數(shù)資料
| 型號： | XA3SD3400A-4FGG676I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 12/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3ADSP FPGA 3400K 676FBGA |
| 產(chǎn)品培訓模塊： | Extended Spartan 3A FPGA Family |
| 標準包裝： | 40 |
| 系列： | Spartan®-3A DSP XA |
| LAB/CLB數(shù)： | 5968 |
| 邏輯元件/單元數(shù)： | 53712 |
| RAM 位總計： | 2322432 |
| 輸入/輸出數(shù)： | 469 |
| 門數(shù)： | 3400000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 676-BGA |
| 供應商設備封裝： | 676-FBGA（27x27） |
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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
2
Refer to DS610, Spartan-3A DSP FPGA Family Data Sheet for a full product description, AC and DC specifications, and
package pinout descriptions. Any values shown specifically in this XA Spartan-3A DSP Automotive FPGA Family data sheet
override those shown in DS610.
For information regarding reliability qualification, refer to RPT103, Xilinx Spartan-3A Family Automotive Qualification Report
and RPT070, Spartan-3A Commercial Qualification Report. Contact your local Xilinx representative for more details on
these reports.
Key Feature Differences from Commercial XC Devices
AEC-Q100 device qualification and full production part approval process (PPAP) documentation support available in
both extended temperature I- and Q-Grades
Guaranteed to meet full electrical specifications over the TJ = –40°C to +125°C temperature range (Q-Grade)
XA Spartan-3A DSP devices are available in the -4 speed grade only
PCI-66 and PCI-X are not supported in the XA Spartan-3A DSP FPGA product line
Platform Flash is not supported within the XA family
XA Spartan-3A DSP devices are available in Pb-free packaging only
MultiBoot is not supported in XA versions of this product.
The XA Spartan-3A DSP device must be power cycled prior to reconfiguration.
Architectural Overview
The XA Spartan-3A DSP family architecture consists of five fundamental programmable functional elements:
XtremeDSP DSP48A Slice provides an 18-bit x 18-bit multiplier, 18-bit pre-adder, 48-bit post-adder/accumulator, and
cascade capabilities for various DSP applications.
Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage
elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data.
Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. IOBs
support bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including several
high-performance differential standards. Double Data-Rate (DDR) registers are included.
Block RAM provides data storage in the form of 18-Kb dual-port blocks.
Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying,
multiplying, dividing, and phase-shifting clock signals.
These elements are organized as shown in Figure 1. A dual ring of staggered IOBs surrounds a regular array of CLBs. The
XA3SD1800A has four columns of DSP48A slices, and the XA3SD3400A has five columns of DSP48A slices. Each
DSP48A has an associated block RAM. The DCMs are positioned in the center with two at the top and two at the bottom of
the device and in the two outer columns of the four or five columns of block RAM and DSP48As.
The XA Spartan-3A DSP family features a rich network of routing that interconnect all five functional elements, transmitting
signals among them. Each functional element has an associated switch matrix that permits multiple connections to the
routing.
Table 1: Summary of XA Spartan-3A DSP FPGA Attributes
Device
System
Gates
Equivalent
Logic
Cells
CLB Array
(One CLB = Four Slices)
Distributed
RAM bits(1)
Block
RAM
Bits
Dedicated
Multipliers
DCMs
Maximum
User I/O
Maximum
Differential
I/O Pairs
Rows Columns
Total
CLBs
Total
Slices
XA3SD1800A 1800K
37,440
88
48
4,160 16,640
260K
1512K
84
8
519
227
XA3SD3400A 3400K
53,712
104
58
5,968 23,872
373K
2268K
126
8
469
213
Notes:
1.
By convention, one Kb is equivalent to 1,024 bits.
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