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參數(shù)資料
| 型號： | XA6SLX9-3FTG256Q |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN 6 256FTGBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Spartan®-6 LX XA |
| LAB/CLB數(shù)： | 715 |
| 邏輯元件/單元數(shù)： | 9152 |
| RAM 位總計： | 589824 |
| 輸入/輸出數(shù)： | 186 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
DS170 (v1.3) December 13, 2012
Product Specification
1
Copyright 2010–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.
General Description
The Xilinx Automotive (XA) Spartan-6 family of FPGAs provides leading system integration capabilities with the lowest total cost for high-
volume automotive applications. The ten-member family delivers expanded densities ranging from 3,840 to 101,261 logic cells and faster,
more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost,
power, and performance, the XA Spartan-6 family offers a new, more efficient, dual-register 6-input look-up table (LUT) logic and a rich
selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM
memory controllers, enhanced mixed-mode clock management blocks, SelectIO technology, power-optimized high-speed serial
transceiver blocks, PCI Express compatible Endpoint blocks, advanced system-level power management modes, auto-detect
configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a low-cost programmable
alternative to custom ASIC products with unprecedented ease of use. XA Spartan-6 FPGAs offer the best solution for flexible and scalable
high-volume logic designs, high-bandwidth parallel DSP processing designs, and cost-sensitive applications where multiple interfacing
standards are required. XA Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver
integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.
Summary of XA Spartan-6 FPGA Features
XA Spartan-6 Family:
XA Spartan-6 LX FPGA: Logic optimized
XA Spartan-6 LXT FPGA: High-speed serial connectivity
Automotive Temperatures:
I-Grade: Tj = –40°C to +100°C
Q-Grade: Tj = –40°C to +125°C
Automotive Standards:
Xilinx is ISO-TS16949 compliant
AEC-Q100 qualification
Production Part Approval Process (PPAP) documentation
Beyond AEC-Q100 qualification is available upon request
Designed for low cost
Multiple efficient integrated blocks
Optimized selection of I/O standards
Staggered pads
High-volume plastic wire-bonded packages
Low static and dynamic power
45 nm process optimized for cost and low power
Hibernate power-down mode for zero power
Suspend mode maintains state and configuration with multi-
pin wake-up, control enhancement
High performance 1.2V core voltage (LX and LXT FPGAs, -2
and -3 speed grades)
Multi-voltage, multi-standard SelectIO interface banks
Up to 1,080 Mb/s data transfer rate per differential I/O
Selectable output drive, up to 24 mA per pin
3.3V to 1.2V I/O standards and protocols
Low-cost HSTL and SSTL memory interfaces
Hot swap compliance
Adjustable I/O slew rates to improve signal integrity
High-speed GTP serial transceivers in the LXT FPGAs
Up to 3.2 Gb/s
High-speed interfaces including: Serial ATA and PCI Express
Efficient DSP48A1 slices
High-performance arithmetic and signal processing
Fast 18 x 18 multiplier and 48-bit accumulator
Pipelining and cascading capability
Pre-adder to assist filter applications
Integrated Memory Controller blocks
DDR, DDR2, DDR3, and LPDDR support
Data rates up to 800 Mb/s
Multi-port bus structure with independent FIFO to reduce
design timing issues
Abundant logic resources with increased logic capacity
Optional shift register or distributed RAM support
Efficient 6-input LUTs improve performance and minimize
power
LUT with dual flip-flops for pipeline centric applications
Block RAM with a wide range of granularity
Fast block RAM with byte write enable
18 Kb blocks that can be optionally programmed as two
independent 9 Kb block RAMs
Clock Management Tile (CMT) for enhanced performance
Low noise, flexible clocking
Digital Clock Managers (DCMs) eliminate clock skew and
duty cycle distortion
Phase-Locked Loops (PLLs) for low-jitter clocking
Frequency synthesis with simultaneous multiplication,
division, and phase shifting
Sixteen low-skew global clock networks
Simplified configuration, supports low-cost standards
2-pin auto-detect configuration
Broad third-party SPI (up to x4) and NOR flash support
MultiBoot support for remote upgrade with multiple
bitstreams, using watchdog protection
Enhanced security for design protection
Unique Device DNA identifier for design authentication
AES bitstream encryption in the XA6SLX75, XA6SLX75T,
and XA6SLX100 devices
Integrated Endpoint block for PCI Express designs (LXT)
Low-cost PCI technology support compatible with the 33 MHz,
32- and 64-bit specification.
Faster embedded processing with enhanced, low cost,
MicroBlaze 32-bit soft processor
Industry-leading IP and reference designs
Strong automotive-specific third-party ecosystem with IP,
development boards, and design services
10
XA Spartan-6 Automotive FPGA
Family Overview
DS170 (v1.3) December 13, 2012
Product Specification
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