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參數(shù)資料
| 型號： | XA6SLX9-3FTG256Q |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN 6 256FTGBGA |
| 標準包裝： | 1 |
| 系列： | Spartan®-6 LX XA |
| LAB/CLB數(shù)： | 715 |
| 邏輯元件/單元數(shù)： | 9152 |
| RAM 位總計： | 589824 |
| 輸入/輸出數(shù)： | 186 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 256-LBGA |
| 供應商設(shè)備封裝： | 256-FTBGA |
XA Spartan-6 Automotive FPGA Family Overview
DS170 (v1.3) December 13, 2012
Product Specification
3
Configuration
XA Spartan-6 FPGAs store the customized configuration data in SRAM-type internal latches. The number of configuration
bits is between 3 Mb and 27 Mb depending on device size and user-design implementation options. The configuration
storage is volatile and must be reloaded whenever the FPGA is powered up. This storage can also be reloaded at any time
by pulling the PROGRAM_B pin Low. Several methods and data formats for loading configuration are available.
Bit-serial configurations can be either master serial mode, where the FPGA generates the configuration clock (CCLK) signal,
or slave serial mode, where the external configuration data source also clocks the FPGA. For byte-wide configurations,
master SelectMAP mode generates the CCLK signal while slave SelectMAP mode receives the CCLK signal for the 8- and
16-bit-wide transfer. In master serial mode, the beginning of the bitstream can optionally switch the clocking source to an
external clock, which can be faster or more precise than the internal clock. The available JTAG pins use boundary-scan
protocols to load bit-serial configuration data.
The bitstream configuration information is generated by the ISE software using a program called BitGen. The configuration
process typically executes the following sequence:
Detects power-up (power-on reset) or PROGRAM_B when Low.
Clears the whole configuration memory.
Samples the mode pins to determine the configuration mode: master or slave, bit-serial or parallel.
Loads the configuration data starting with the bus-width detection pattern followed by a synchronization word, checks
for the proper device code, and ends with a cyclic redundancy check (CRC) of the complete bitstream.
Starts a user-defined sequence of events: releasing the internal reset (or preset) of flip-flops, optionally waiting for the
DCMs and/or PLLs to lock, activating the output drivers, and transitioning the DONE pin to High.
The Master Serial Peripheral Interface (SPI) and the Master Byte-wide Peripheral Interface (BPI) are two common methods
used for configuring the devices. The XA Spartan-6 FPGA configures itself from a directly attached industry-standard SPI
serial flash PROM. The XA Spartan-6 FPGA can configure itself via BPI when connected to an industry-standard parallel
NOR flash. Note that BPI configuration is not supported in the XA6SLX4, XA6SLX25, and XA6SLX25T.
XA Spartan-6 FPGAs support MultiBoot configuration, where two or more FPGA configuration bitstreams can be stored in
a single configuration source. The FPGA application controls which configuration to load next and when to load it.
XA Spartan-6 FPGAs also include a unique, factory-programmed Device DNA identifier that is useful for tracking purposes,
anti-cloning designs, or IP protection. In the XA6SLX75, XA6SLX75T, and XA6SLX100 devices, bitstreams can be copy
protected using AES encryption.
Readback
Most configuration data can be read back without affecting the system’s operation.
CLBs, Slices, and LUTs
Each configurable logic block (CLB) in XA Spartan-6 FPGAs consists of two slices, arranged side-by-side as part of two
vertical columns. There are three types of CLB slices in the XA Spartan-6 architecture: SLICEM, SLICEL, and SLICEX.
Each slice contains four LUTs, eight flip-flops, and miscellaneous logic. The LUTs are for general-purpose combinatorial and
sequential logic support. Synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features.
Expert designers can also instantiate them.
SLICEM
One quarter (25%) of the XA Spartan-6 FPGA slices are SLICEMs. Each of the four SLICEM LUTs can be configured as
either a 6-input LUT with one output, or as dual 5-input LUTs with identical 5-bit addresses and two independent outputs.
These LUTs can also be used as distributed 64-bit RAM with 64 bits or two times 32 bits per LUT, as a single 32-bit shift
register (SRL32), or as two 16-bit shift registers (SRL16s) with addressable length. Each LUT output can be registered in a
flip-flop within the CLB. For arithmetic operations, a high-speed carry chain propagates carry signals upwards in a column
of slices.
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