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參數(shù)資料
| 型號(hào)： | XC17256EVO8I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 2/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SERIAL CFG PROM 256K 8-SOIC |
| 產(chǎn)品變化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 Product Discontinuation 28/Jul/2010 |
| 標(biāo)準(zhǔn)包裝： | 98 |
| 可編程類型： | OTP |
| 存儲(chǔ)容量： | 256Kb |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-TSOP |
| 包裝： | 管件 |
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XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DS027 (v3.5) June 25, 2008
Product Specification
10
R
AC Characteristics Over Operating Condition When Cascading
Symbol
Description
XC1701,
XC17128E,
XC17256E,
XC1704L,
XC1702L
XC17128EL,
XC17256EL,
XC1701L,
XC17512L
XC1736E,
XC1765E
XC1765EL
Units
Min
Max
Min
Max
Min
Max
Min
Max
TCDF
CLK to data float delay(2,3)
–50–50–50–50
ns
TOCK
CLK to CEO delay(3)
–30–30–30–30
ns
TOCE
CE to CEO delay(3)
–35–35–35–35
ns
TOOE
RESET/OE to CEO delay(3)
–30–30–30–30
ns
TCCE
CE to data delay when cascading
–
45
–
90
–
60
–
110
ns
Notes:
1.
AC test load = 50 pF.
2.
Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3.
Guaranteed by design, not tested.
4.
All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
5.
For cascaded PROMs:
- TCYC min = TOCK + TCCE + FPGA data setup time (TDCC/TDSCK).
Example: If the XC1701L is cascaded to configure an FPGA TDCC = 5 sec, then the actual TCYC min = 30 ns + 90 ns + 5 ns = 125 ns,
or max CLK frequency = 8 MHz.
- TCAC max = TOCK + TCCE.
Example: For the XC1701L when cascading, the actual TCAC max = 30 ns + 90 ns = 120 ns.
RESET/OE
CLK
DATA
(First PROM)
DATA
(Cascaded
PROM)
CE
CEO
(First PROM)
CE
(Cascaded
PROM)
Last
Bit
Last
Bit
First
Bit
First
Bit
DS027_04_071204
n
nn +1
n –1
TCDF
TOOE
TOCK
TOCE
TCCE
Product Obsolete or Under Obsolescence
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