參數(shù)資料
型號(hào)： XC17512LPC20C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 8/13頁(yè)
文件大?。?/td> 0K
描述： IC PROM SER C-TEMP 512K 20-PLCC
產(chǎn)品變化通告： Product Discontinuation 28/Jul/2010
標(biāo)準(zhǔn)包裝： 46
可編程類型： OTP
存儲(chǔ)容量： 512kb
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
封裝/外殼： 20-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 20-PLCC
包裝： 管件
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DS027 (v3.5) June 25, 2008
Product Specification
4
R
Xilinx FPGAs and Compatible PROMs
Controlling PROMs
Connecting the FPGA device with the PROM:
The DATA output(s) of the of the PROM(s) drives the
DIN input of the lead FPGA device.
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a VCC glitch.
Other methods—such as driving RESET/OE from LDC
or system reset—assume the PROM internal power-
on-reset is always in step with the FPGA’s internal
power-on-reset. This may not be a safe assumption.
The PROM CE input can be driven from either the LDC
or DONE pins. Using LDC avoids potential contention
on the DIN pin.
The CE input of the lead (or only) PROM is driven by
the DONE output of the lead FPGA device, provided
that DONE is not permanently grounded. Otherwise,
LDC can be used to drive CE, but must then be
unconditionally High during user operation. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
Device
Configuration
Bits
PROM
XC4003E
53,984
XC17128E(1)
XC4005E
95,008
XC17128E
XC4006E
119,840
XC17128E
XC4008E
147,552
XC17256E
XC4010E
178,144
XC17256E
XC4013E
247,968
XC17256E
XC4020E
329,312
XC1701
XC4025E
422,176
XC1701
XC4002XL
61,100
XC17128EL(1)
XC4005XL
151,960
XC17256EL
XC4010XL
283,424
XC17512L
XC4013XL/XLA
393,632
XC17512L
XC4020XL/XLA
521,880
XC17512L
XC4028XL/XLA
668,184
XC1701L
XC4028EX
668,184
XC1701
XC4036EX/XL/XLA
832,528
XC1701L
XC4036EX
832,528
XC1701
XC4044XL/XLA
1,014,928
XC1701L
XC4052XL/XLA
1,215,368
XC1702L
XC4062XL/XLA
1,433,864
XC1702L
XC4085XL/XLA
1,924,992
XC1702L
XC40110XV
2,686,136
XC1704L
XC40150XV
3,373,448
XC1704L
XC40200XV
4,551,056
XC1704L +
XC17512L
XC40250XV
5,433,888
XC1704L+
XC1702L
XC5202
42,416
XC1765E
XC5204
70,704
XC17128E
XC5206
106,288
XC17128E
XC5210
165,488
XC17256E
XC5215
237,744
XC17256E
XCV50
559,200
XC1701L
XCV100
781,216
XC1701L
XCV150
1,040,096
XC1701L
XCV200
1,335,840
XC1702L
XCV300
1,751,808
XC1702L
XCV400
2,546,048
XC1704L
XCV600
3,607,968
XC1704L
XCV800
4,715,616
XC1704L +
XC1701L
XCV1000
6,127,744
XC1704L +
XC1702L
XCV50E
630,048
XC1701L
XCV100E
863,840
XC1701L
XCV200E
1,442,016
XC1702L
XCV300E
1,875,648
XC1702L
XCV400E
2,693,440
XC1704L
XCV405E
3,340,400
XC1704L
XCV600E
3,961,632
XC1704L
XCV812E
6,519,648
2 of XC1704L
XCV1000E
6,587,520
2 of XC1704L
XCV1600E
8,308,992
2 of XC1704L
XCV2000E
10,159,648
3 of XC1704L
XCV2600E
12,922,336
4 of XC1704L
XCV3200E
16,283,712
4 of XC1704L
Notes:
1.
The suggested PROM is determined by compatibility with the
higher configuration frequency of the Xilinx FPGA CCLK.
Designers using the default slow configuration frequency (CCLK)
can use the XC1765E or XC1765EL for the noted FPGA devices.
Device
Configuration
Bits
PROM
Product Obsolete or Under Obsolescence
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