參數(shù)資料
型號: XC2C384-7FGG324C
廠商: Xilinx Inc
文件頁數(shù): 5/16頁
文件大?。?/td> 0K
描述: IC CR-II CPLD 384MCELL 324-FBGA
標(biāo)準(zhǔn)包裝: 60
系列: CoolRunner II
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 7.1ns
電壓電源 - 內(nèi)部: 1.7 V ~ 1.9 V
邏輯元件/邏輯塊數(shù)目: 24
宏單元數(shù): 384
門數(shù): 9000
輸入/輸出數(shù): 240
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 324-BBGA
供應(yīng)商設(shè)備封裝: 324-FBGA(23x23)
包裝: 托盤
CoolRunner-II CPLD Family
DS090 (v3.1) September 11, 2008
13
Product Specification
R
to be programmed at any time. All devices are shipped in
the erased state from the factory.
Applying power to a blank part might result in a higher cur-
rent flow as the part initializes. This behavior is normal and
might persist for approximately 2 seconds, depending on
the power supply ramp.
If the device is programmed, the device inputs and outputs
take on their configured states for normal operation. The
JTAG pins are enabled to allow device erasure or bound-
ary-scan tests at any time.
I/O Banking
CoolRunner-II CPLD XC2C32A and XC2C64A macrocell
parts support two VCCIO rails that can range from 3.3V
down to 1.5V operation. Two VCCIO rails are supported on
the 128 and 256 macrocell parts where outputs on each rail
can independently range from 3.3V down to 1.5V operation.
Four VCCIO rails are supported on the 384 and 512 macro-
cell parts. Any of the VCCIO rails can assume any one of the
VCCIO values of 1.5V, 1.8V, 2.5V, or 3.3V. Designers should
assign input and output voltages to a bank with VCCIO set at
the voltage range of that input or output voltage. The VCC
(internal supply voltage) for a CoolRunner-II CPLD must be
maintained within 1.8V ±5% for correct speed operation and
proper in system programming.
Mixed Voltage, Power Sequencing, and
Hot Plugging
As mentioned in I/O Banking, CoolRunner-II CPLD parts
support mixed voltage I/O signals. It is important to assign
signals to an I/O bank with the appropriate I/O voltage. Driv-
ing a high voltage into a low voltage bank can result in neg-
ative current flow through the power supply pins. The power
applied to the VCCIO and VCC pins can occur in any order
and the CoolRunner-II CPLD will not be damaged. For best
results, Xilinx recommends that VCCINT be applied before
VCCIO To ensure that the internal logic is correct before the
I/Os are active. CoolRunner-II CPLDs can reside on boards
where the board is inserted into a “l(fā)ive” connector (hot
plugged) and the parts will be well-behaved as if powering
up in a standard way.
Development System Support
Xilinx CoolRunner-II CPLDs are supported by all configura-
tions of Xilinx standard release development software as
well as the freely available ISE WebPACK software avail-
able from www.xilinx.com. Third party development tools
include synthesis tools from Cadence, Exemplar, Mentor
Graphics, Synplicity, and Synopsys.
ATE Support
Third party ATE development support is available for both
programming and board/chip level testing. Vendors provid-
ing this support include Agilent, GenRad, and Teradyne.
Other third party providers are expected to deliver solutions
in the future.
Figure 12: Device Behavior During Power Up
VCCINT
No
Power
3.8 V
(Typ)
0V
No
Power
Quiescent
State
Quiescent
State
User Operation
Initialization Transition of User Array
x382_10
1.3V
(Typ)
Table 8: I/O Power-Up Characteristics
Device Circuitry
Quiescent State
Erased Device Operation
Valid User Operation
IOB Bus-Hold/Weak Pullup
Weak Pull-up
Bus-Hold/Weak Pullup
Device Outputs
Disabled
As Configured
Device Inputs and Clocks
Disabled
As Configured
Function Block
Disabled
As Configured
JTAG Controller
Disabled
Enabled
相關(guān)PDF資料
PDF描述
TAJT106M016RNJ CAP TANT 10UF 16V 20% 1210
GCC08DCMN CONN EDGECARD 16POS .100" WW
XC2C512-10PQG208I IC CR-II CPLD 512MCRCELL 208PQFP
PQ1L333M2SP IC REG LDO 3.3V .3A SOT-89
TAJT106M010YNJ CAP TANT 10UF 10V 20% 1210
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2C384-7FT256C 制造商:Xilinx 功能描述:CPLD COOLRUNNER-II 9K GATES 384 MCRCLLS 350MHZ 0.18UM 1.8V 2 - Trays 制造商:Xilinx 功能描述:IC CR-II CPLD 384MCELL 256-FBGA
XC2C384-7FTG256C 功能描述:IC CRII CPLD 384MCRCELL 256BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD(復(fù)雜可編程邏輯器件) 系列:CoolRunner II 標(biāo)準(zhǔn)包裝:40 系列:ispMACH® 4000C 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):5.0ns 電壓電源 - 內(nèi)部:1.65 V ~ 1.95 V 邏輯元件/邏輯塊數(shù)目:32 宏單元數(shù):512 門數(shù):- 輸入/輸出數(shù):128 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:176-LQFP 供應(yīng)商設(shè)備封裝:176-TQFP(24x24) 包裝:托盤
XC2C384-7PQ208C 制造商:Xilinx 功能描述:CPLD COOLRUNNER-II 9K GATES 384 MCRCLLS 350MHZ 0.18UM 1.8V 2 - Trays 制造商:Xilinx 功能描述:IC CPLD 384MC 7.1NS 208PQFP
XC2C384-7PQG208C 功能描述:IC CR-II CPLD 384MCELL 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD(復(fù)雜可編程邏輯器件) 系列:CoolRunner II 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP(28x28) 包裝:托盤
XC2C384-7TQ144C 制造商:Xilinx 功能描述:CPLD COOLRUNNER-II 9K GATES 384 MCRCLLS 350MHZ 0.18UM 1.8V 1 - Trays 制造商:Xilinx 功能描述:IC CR-II CPLD 384MCELL 144-TQFP 制造商:Xilinx 功能描述:IC CPLD 384MC 7.1NS 144TQFP