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參數(shù)資料
| 型號： | XC2C64SERIES |
| 英文描述： | CoolRunner-II CPLD |
| 中文描述： | 的CoolRunner - II CPLD實(shí)現(xiàn) |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 95K |
| 代理商： | XC2C64SERIES |
DS092 (v1.0) January 3, 2002
Advance Product Specification
1-800-255-77781
2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
Optimized for 1.8V systems
-
Industry’s fastest low power CPLD
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Static Icc of less than 100 microamps at all times
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Densities from 32 to 512 macrocells
Industry’s best 0.18 micron CMOS CPLD
-
Optimized architecture for effective logic synthesis
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Multi-voltage I/O operation — 1.5V to 3.3V
Available in multiple package options
-
44-pin PLCC with 33 user I/O
-
44-pin VQFP with 33 user I/O
-
56-ball CP (0.05mm) BGA with 45 user I/O
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100-pin VQFP with 64 user I/O
Advanced system features
-
Fastest in system programming
·
1.8V ISP using IEEE 1532 (JTAG) interface
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IEEE1149.1 JTAG Boundary Scan Test
-
Optional Schmitt trigger input (per pin)
-
Unsurpassed low power management
-
FZP 100% CMOS product term generation
-
Flexible clocking modes
·
Optional DualEDGE triggered registers
-
Global signal options with macrocell control
·
Multiple global clocks with phase selection per
macrocell
·
Multiple global output enables
·
Global set/reset
-
Abundant product term clocks, output enables and
set/resets
-
Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
-
Advanced design security
-
Open-drain output option for Wired-OR and LED
drive
-
Optional bus-hold or weak pullup on selected I/O
pins
-
Optional configurable grounds on unused I/Os
-
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels on all parts
-
PLA architecture
·
Superior pinout retention
·
100% product term routability across function
block
-
Hot pluggable
-
Design entry/verification using Xilinx and industry
standard CAE tools
-
Free software support for all densities using Xilinx
WebPACK
or WebFITTER
tools
Industry leading nonvolatile 0.18 micron CMOS
process
Guaranteed 1,000 program/erase cycles
Guaranteed 20 year data retention
Refer to the CoolRunner
-II family data sheet for architec-
ture description.
-
-
-
Description
The CoolRunner-II 64-macrocell device is designed for both
high performance and low power applications. This lends
power savings to high-end communication equipment and
high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved
This device consists of four Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output
control signals include slew rate control, bus hold and open
drain. A Schmitt trigger input is available on a per input pin
basis. In addition to combinatorial and registered outputs,
the registers may be configured as fast inputs.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. These clocks are additionally
used to set or preset individual macrocell registers on
power up. Local clocks are generated in specific Function
Blocks and only available to macrocell registers in that
Function Block.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows performance where it is
needed without raising the total power consumption of the
entire device.
The CoolRunner-II 64-macrocell CPLD is I/O compatible
with standard LVTTL33 and LVCMOS18, 25, and 33 volts
(see Table 1). This device is also 1.5 volt I/O compatible
with the use of Schmitt inputs.
0
XC2C64 CoolRunner-II CPLD
DS092 (v1.0) January 3, 2002
0
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Advance Product Specification
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