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參數(shù)資料
| 型號： | XC2C64SERIES |
| 英文描述： | CoolRunner-II CPLD |
| 中文描述： | 的CoolRunner - II CPLD實(shí)現(xiàn) |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 95K |
| 代理商： | XC2C64SERIES |
XC2C64 CoolRunner-II CPLD
2
1-800-255-7778Advance Product SpecificationR
Fast Zero Power Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
Fast Zero Power
(FZP), a design technique that makes
use of CMOS technology in both the fabrication and design
methodology. FZP design technology employs a cascade of
CMOS gates to implement sum of products instead of tradi-
tional sense amplifier methodology. Due to this technology,
Xilinx CoolRunner-II CPLDs achieve both high performance
and low power operation.
Supported I/O Standards
The CoolRunner-II 64 macrocell features both LVCMOS
and LVTTL I/O implementations. See
Table 1
for I/O stan-
dard voltages. The LVTTL I/O standard is a general purpose
EIA/JESDSA standard for 3.3V applications that use an
LVTTL input buffer and Push-Pull output buffer. The LVC-
MOS standard is used in 3.3V, 2.5V, 1.8V applications.
CoolRunner-II CPLDs are also 1.5V I/O compatible with the
use of Schmitt inputs.
Table 1:
I/O Standards for XC2C64
I/O
Standard
Output
V
CCIO
3.3V
Input
V
CCIO
3.3V
Input
V
REF
N/A
Board
Termination
Voltage V
T
N/A
LVTTL
LVCMOS33
3.3
3.3
N/A
N/A
LVCMOS25
2.5
2.5
N/A
N/A
LVCMOS18
1.8
1.8
N/A
N/A
Figure 1:
I
CC
vs Frequency
Table 2:
I
CC
vs Frequency (LVCMOS 1.8V T
A
= 25°C)
(1)
Frequency (MHz)
50
75
100
125
150
175
200
225
250
275
300
Typical I
CC
(mA)
3.6
5.5
7.3
9.1
10.8
12.5
14.2
15.9
17.5
19.2
20.8
Notes:
1.
16-bit up/down, resettable binary counter (one counter per function block).
Frequency (MHz)
DS092_07_121501
I
0
0
5
10
15
20
25
300
250
200
150
100
50
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