參數(shù)資料
型號(hào)： XC2S150-5FG456I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 6/99頁(yè)
文件大小： 0K
描述： IC FPGA 2.5V I-TEMP 456-FBGA
標(biāo)準(zhǔn)包裝： 60
系列： Spartan®-II
LAB/CLB數(shù)： 864
邏輯元件/單元數(shù)： 3888
RAM 位總計(jì)： 49152
輸入/輸出數(shù)： 260
門(mén)數(shù)： 150000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 456-BBGA
供應(yīng)商設(shè)備封裝： 456-FBGA
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
14
R
Boundary-scan operation is independent of individual IOB
configurations, and unaffected by package type. All IOBs,
including unbonded ones, are treated as independent
3-state bidirectional pins in a single scan chain. Retention of
the bidirectional test capability after configuration facilitates
the testing of external interconnections.
Table 7 lists the boundary-scan instructions supported in
Spartan-II FPGAs. Internal signals can be captured during
EXTEST by connecting them to unbonded or unused IOBs.
They may also be connected to the unused outputs of IOBs
defined as unidirectional input pins.
The public boundary-scan instructions are available prior to
configuration. After configuration, the public instructions
remain available together with any USERCODE
instructions installed during the configuration. While the
SAMPLE and BYPASS instructions are available during
configuration, it is recommended that boundary-scan
operations not be performed during this transitional period.
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the FPGA,
and also to read back the configuration data.
To facilitate internal scan chains, the User Register
provides three outputs (Reset, Update, and Shift) that
represent the corresponding states in the boundary-scan
internal state machine.
Table 7: Boundary-Scan Instructions
Boundary-Scan
Command
Binary
Code[4:0]
Description
EXTEST
00000
Enables boundary-scan
EXTEST operation
SAMPLE
00001
Enables boundary-scan
SAMPLE operation
USR1
00010
Access user-defined
register 1
USR2
00011
Access user-defined
register 2
CFG_OUT
00100
Access the
configuration bus for
Readback
CFG_IN
00101
Access the
configuration bus for
Configuration
INTEST
00111
Enables boundary-scan
INTEST operation
USRCODE
01000
Enables shifting out
USER code
IDCODE
01001
Enables shifting out of
ID Code
HIZ
01010
Disables output pins
while enabling the
Bypass Register
JSTART
01100
Clock the start-up
sequence when
StartupClk is TCK
BYPASS
11111
Enables BYPASS
RESERVED
All other
codes
Xilinx reserved
instructions
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