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參數(shù)資料
| 型號(hào)： | XC2S200-5 |
| 元件分類(lèi)： | 通信、網(wǎng)絡(luò)模塊及開(kāi)發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大小： | 115K |
| 代理商： | XC2S200-5 |
May 20, 2002
3
Memec Design
Applications
Scanners
Printers
Mass Storage
General Description
The Universal Serial Bus (USB) Device Controller core pro-
vides an interface between the USB Function Device and
the USB Host Controller. This FPGA implementation is
based upon inSilicon's highly successful USB Core. The
core supports both full-speed and low-speed modes. The
application interface is inSilicon
’
s TymeWare
Virtual
Component Interface (VCI), which is fully compliant with
the VSI Alliance
Virtual Component Interface Standard
(OCB 2 1.0). The USB core handles all USB protocol and
provides a simple read/write protocol for the function inter-
face (application bus). The USB core does not have FIFOs
built in, enabling you to define FIFO requirements.
Functional Description
Phase Lock Loop (PLL) Block
The PLL block is a digital phase lock loop, which extracts
the clock and data from the USB cable. Input to the PLL
block is from the USB differential transceiver.
Serial Interface Engine (SIE) Block
The SIE block handles the front-end functions of the USB
protocol such as SyncField identification, NRZI-NRZ con-
version, token packet decoding, bit stripping, bit stuffing
NRZ-NRZI conversion, CRC-5 checking, and CRC-16 gen-
eration and checking. The SIE block also converts the
serial data coming in the data packet into 8-bit parallel data.
USB Bridge Layer (UBL) Block
The UBL block handles the error recovery mechanism dur-
ing transactions and interfaces to the device logic. It also
maintains all endpoint information supported by the device.
The UBL also handles all of the control transfers addressed
to endpoint 0. The UBL block is further sub-divided into the
protocol layer (PL) and endpoint (EP) layer blocks. The PL
block controls the SIE block by providing the necessary
handshake signals to the SIE and talks to the device inter-
face logic. It also has the mechanism for error recovery if
the device interface violates the data transfer protocol. The
EP block has all the endpoint-related information and han-
dles all the control transfers to endpoint 0. The EP block
handles all of the USB standard commands.
Virtual Component Interface (VCI) Block
inSilicon's TymeWare VCI block provides the VSI Alliance-
approved interface to the application or system bus. The
VCI contains two sub-blocks: the Control/Status register
(CSR) and VCI State Machine.
The CSR contains all the Control and Status registers that
are essential for core operation. It also contains the
EEPROM controller for reading external EEPROM and pro-
gramming the registers. This block stores each endpoint's
information regarding packet size, type, and direction. It
also registers the pointers from where the descriptors are
to be read when the Get Descriptor command is received.
The VCI State Machine transfers data from/to the applica-
tion with VCI read/write commands. This device runs on the
application interface system clock provided by the user.
The VCI generates read cycles to fetch endpoint data from
the application, transfers the received data from the core to
the application by generating write cycles, and generates a
Status write to the application.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S200-5CS144C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II FPGA Family |
| XC2S200-5CS144I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II FPGA Family |
| XC2S200-5CSG144C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II FPGA Family |
| XC2S200-5CSG144I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II FPGA Family |
| XC2S2005FG256C | 制造商:Xilinx 功能描述: |
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