- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371311 > XC2S200-5 Telecomm/Datacomm PDF資料下載
參數(shù)資料
| 型號： | XC2S200-5 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 115K |
| 代理商： | XC2S200-5 |
MC-XIL-USB11DEV USB 1.1 Device Controller
4
May 20, 2002
Pinout
The pinout of the USB 1.1 Device Controller core has not
been fixed to specific FPGA I/O, allowing flexibility with a
user
’
s application. The signal names are shown in Figure 1
and described in Table 2.
Table 2: Core Signal Pinout
Signal Name
Direction
Description
Clock and Reset signals
app_clk
In
This is the free-running system clock provided by the application. The
signal on the application bus are synchronous to this clock.
This is the 12-/1.5-Mhz clock input
This reset signal is synchronous to the application clock. When
rst_appclk is asserted, all core flip-flops and registers that run on the ap-
plication clock switch to the default state.
This reset signal is synchronous to the dev_clk signal.
This is the external clock used in the DPLL to extract clock and data in-
formation from the USB cable.
This clock is obtained by dividing the clk_4x by four in the DPLL block.
This is the recovered clock for the DPLL.
The user must connect the pll_clk_out signal to this input.
This signal resets the clock extraction and the clk_1x generation logic in
the DPLL block.
dev_clk
rst_appclk
In
In
rst_dev_clk
clk_4x
In
In
clk_1x
pll_clock_out
pll_clk_in
pll_reset
Out
Out
In
In
DPLL and Transceiver Interface Signals
dpls
dmns
xver_data
In
In
In
This is the D+ (dpls) signal from the USB.
This is the D- (dmns) signal from the USB.
This is the data from the differential receiver. The dpls and dmns signals
are passed through the differential receivers to extract the data.
The is the data to be driven on dpls.
This is the data to be driven on dmns.
This is the transmission-enable signal to drive the ucvi_txdpls and
udcvci_txdpls and udcvci_txdmns signals onto the cable.
This is the Resume generation signal from the application.
This is the STALL generation signal indication from the application.
udcvci_txdpls
udcvci_txdmns
udcvci_txen
Out
Out
Out
app_resume
app_stall
Strap Signals
app_speed
In
In
In
This indicates the application speed. HIGH indicates full-speed opera-
tion (12 Mbps) and LOW indicates low-speed operation (1.5 Mbps)
This is the device Remote Wakeup capability input pin.
This is the power status signal.
Supports the Set Descriptor command.
Synch Frame command support
Initializes incremental address interface support.
app_rmtwkup
app_self_pwr
app_setdesc_sup
app_synccmd_sup
app_ram_if_sup
Data Interface Signals
udcvci_cmdvalid
udcvci_addr[15:0]
udcvci_rnw
In
In
In
In
In
Out
Out
Out
This is asserted by the core to indicate the start of a transaction.
This is the encoded address pointer for the current data transfer.
This indicates whether the current transaction is a read or a write trans-
action.
This is the write data for the VCI transaction.
This indicates the valid bytes in the 32 bits of udcvci_data.
This indicates that the current transaction is a Burst transaction.
udcvci_data[31:0]
udcvci_ben[3:0]
udcvci_burst
Out
Out
Out
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC2S300E-8 | Telecomm/Datacomm |
| XC2S400E-6FG456C | FPGA |
| XC2S400E-6FG456I | FPGA |
| XC2S400E-6FG676C | FPGA |
| XC2S400E-6FG676I | FPGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S200-5CS144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S200-5CS144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S200-5CSG144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S200-5CSG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S2005FG256C | 制造商:Xilinx 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。