參數(shù)資料
型號(hào)： XC2S400E-7FG456C
英文描述： FPGA
中文描述： FPGA的
文件頁(yè)數(shù)： 9/21頁(yè)
文件大?。?/td> 183K
代理商： XC2S400E-7FG456C
Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics
DS077-3 (v2.0) November 18, 2002
Product Specification
www.xilinx.com
1-800-255-7778
9
R
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in
IOB Output Delay Adjustments for Different Standards(1)
, page 10
.
Symbol
Description
Speed Grade
Units
-7
-6
Min
Max
Min
Max
Propagation Delays
T
IOOP
T
IOOLP
O input to pad
1.0
2.7
1.0
2.9
ns
O input to pad via transparent latch
1.2
3.1
1.2
3.4
ns
3-state Delays
T
IOTHZ
T
IOTON
T
IOTLPHZ
T
IOTLPON
T
GTS
T input to pad high impedance
(1)
0.7
1.7
0.7
1.9
ns
T input to valid data on pad
1.1
2.9
1.1
3.1
ns
T input to pad high mpedance via transparent latch
(1)
0.8
2.0
0.8
2.2
ns
T input to valid data on pad via transparent latch
1.2
3.2
1.2
3.4
ns
GTS to pad high impedance
(1)
1.9
4.6
1.9
4.9
ns
Sequential Delays
T
IOCKP
T
IOCKHZ
T
IOCKON
Clock CLK to pad
0.9
2.8
0.9
2.9
ns
Clock CLK to pad high impedance (synchronous)
(1)
0.7
2.0
0.7
2.2
ns
Clock CLK to valid data on pad (synchronous)
1.1
3.2
1.1
3.4
ns
Setup/Hold Times with Respect to Clock CLK
T
IOOCK
/ T
IOCKO
T
IOOCECK
/ T
IOCKOCE
T
IOSRCKO
/ T
IOCKOSR
T
IOTCK
/ T
IOCKT
T
IOTCECK
/ T
IOCKTCE
T
IOSRCKT
/ T
IOCKTSR
Set/Reset Delays
O input
1.0 / 0
-
1.1 / 0
-
ns
OCE input
0.7 / 0
-
0.7 / 0
-
ns
SR input (OFF)
0.9 / 0
-
1.0 / 0
-
ns
3-state setup times, T input
0.6 / 0
-
0.7 / 0
-
ns
3-state setup times, TCE input
0.6 / 0
-
0.8 / 0
-
ns
3-state setup times, SR input (TFF)
0.9 / 0
-
1.0 / 0
-
ns
T
IOSRP
T
IOSRHZ
T
IOSRON
T
IOGSRQ
SR input to pad (asynchronous)
1.2
3.3
1.2
3.5
ns
SR input to pad high impedance (asynchronous)
(1)
1.0
2.4
1.0
2.7
ns
SR input to valid data on pad (asynchronous)
1.4
3.7
1.4
3.9
ns
GSR to pad
3.8
8.5
3.8
9.7
ns
Notes:
1.
Three-state turn-off delays should not be adjusted.
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