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參數(shù)資料
| 型號(hào)： | XC2V500-5FGG456I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 256/318頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA VIRTEX-II 500K 456-FBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Virtex®-II |
| LAB/CLB數(shù)： | 768 |
| RAM 位總計(jì)： | 589824 |
| 輸入/輸出數(shù)： | 264 |
| 門數(shù)： | 500000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 456-BBGA |
| 供應(yīng)商設(shè)備封裝： | 456-FBGA |
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Virtex-II Platform FPGAs: Functional Description
R
DS031-2 (v3.5) November 5, 2007
Module 2 of 4
Product Specification
34
Creating a Design
Creating Virtex-II designs is easy with Xilinx Integrated Syn-
thesis Environment (ISE) development systems, which sup-
port advanced design capabilities, including ProActive
Timing Closure, integrated logic analysis, and the fastest
place and route runtimes in the industry. ISE solutions
enable designers to get the performance they need, quickly
and easily.
As a result of the ongoing cooperative development efforts
between Xilinx and EDA Alliance partners, designers can
take advantage of the benefits provided by EDA technolo-
gies in the programmable logic design process. Xilinx devel-
opment systems are available in a number of easy to use
configurations, collectively known as the ISE Series.
ISE Alliance
The ISE Alliance solution is designed to plug and play within
an existing design environment. Built using industry standard
data formats and netlists, these stable, flexible products
enable Alliance EDA partners to deliver their best design
automation capabilities to Xilinx customers, along with the
time to market benefits of ProActive Timing Closure.
ISE Foundation
The ISE Foundation solution delivers the benefits of true
HDL-based design in a seamlessly integrated design envi-
ronment. An intuitive project navigator, as well as powerful
HDL design and two HDL synthesis tools, ensure that
high-quality results are achieved quickly and easily. The ISE
Foundation product includes:
State Diagram entry using Xilinx StateCAD
Automatic HDL Testbench generation using Xilinx
HDLBencher
HDL Simulation using ModelSim XE
Design Flow
Virtex-II design flow proceeds as follows:
Design Entry
Synthesis
Implementation
Verification
Most programmable logic designers iterate through these
steps several times in the process of completing a design.
Design Entry
All Xilinx ISE development systems support the mainstream
EDA design entry capabilities, ranging from schematic
design to advanced HDL design methodologies. Given the
high densities of the Virtex-II family, designs are created
most efficiently using HDLs. To further improve their time to
market, many Xilinx customers employ incremental, modu-
lar, and Intellectual Property (IP) design techniques. When
properly used, these techniques further accelerate the logic
design process.
To enable designers to leverage existing investments in
EDA tools, and to ensure high performance design flows,
Xilinx jointly develops tools with leading EDA vendors,
including:
Aldec
Cadence
Exemplar
Mentor Graphics
Model Technology
Synopsys
Synplicity
Complete information on Alliance Series partners and their
associated design flows is available at www.xilinx.com on
the Xilinx Alliance Series web page.
The ISE Foundation product offers schematic entry and
HDL design capabilities as part of an integrated design
solution - enabling one-stop shopping. These capabilities
are powerful, easy to use, and they support the full portfolio
of Xilinx programmable logic devices. HDL design capabil-
ities include a color-coded HDL editor with integrated lan-
guage templates, state diagram entry, and Core generation
capabilities.
Synthesis
The ISE Alliance product is engineered to support
advanced design flows with the industry's best synthesis
tools. Advanced design methodologies include:
Physical Synthesis
Incremental synthesis
RTL floorplanning
Direct physical mapping
The ISE Foundation product seamlessly integrates synthesis
capabilities purchased directly from Exemplar, Synopsys, and
Synplicity. In addition, it includes the capabilities of Xilinx
Synthesis Technology.
A benefit of having two seamlessly integrated synthesis
engines within an ISE design flow is the ability to apply alter-
native sets of optimization techniques on designs, helping to
ensure that designers can meet even the toughest timing
requirements.
Design Implementation
The ISE Series development systems include Xilinx tim-
ing-driven implementation tools, frequently called “place
and route” or “fitting” software. This robust suite of tools
enables the creation of an intuitive, flexible, tightly inte-
grated design flow that efficiently bridges “l(fā)ogical” and
“physical” design domains. This simplifies the task of defin-
ing a design, including its behavior, timing requirements,
and optional layout (or floorplanning), as well as simplifying
the task of analyzing reports generated during the imple-
mentation process.
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