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參數(shù)資料
| 型號(hào)： | XC2V6000-4BF957C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 113/318頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX II 3M 957-FCBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-II |
| LAB/CLB數(shù)： | 8448 |
| RAM 位總計(jì)： | 2654208 |
| 輸入/輸出數(shù)： | 684 |
| 門數(shù)： | 6000000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 957-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 957-FCBGA（40x40） |
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Virtex-II Platform FPGAs: Functional Description
R
DS031-2 (v3.5) November 5, 2007
Module 2 of 4
Product Specification
12
Configurable Logic Blocks (CLBs)
The Virtex-II configurable logic blocks (CLB) are organized
in an array and are used to build combinatorial and synchro-
nous logic designs. Each CLB element is tied to a switch
matrix to access the general routing matrix, as shown in
Figure 14. A CLB element comprises 4 similar slices, with
fast local feedback within the CLB. The four slices are split
in two columns of two slices with two independent carry
logic chains and one common shift chain.
Slice Description
Each slice includes two 4-input function generators, carry
logic, arithmetic logic gates, wide function multiplexers and
two storage elements. As shown in Figure 15, each 4-input
function generator is programmable as a 4-input LUT, 16
bits of distributed SelectRAM memory, or a 16-bit vari-
able-tap shift register element.
The output from the function generator in each slice drives
both the slice output and the D input of the storage element.
Figure 16 shows a more detailed view of a single slice.
Configurations
Look-Up Table
Virtex-II function generators are implemented as 4-input
look-up tables (LUTs). Four independent inputs are pro-
vided to each of the two function generators in a slice (F and
G). These function generators are each capable of imple-
menting any arbitrarily defined boolean function of four
inputs. The propagation delay is therefore independent of
the function implemented. Signals from the function gener-
ators can exit the slice (X or Y output), can input the XOR
dedicated gate (see arithmetic logic), or input the carry-logic
multiplexer (see fast look-ahead carry logic), or feed the D
input of the storage element, or go to the MUXF5 (not
shown in Figure 16).
In addition to the basic LUTs, the Virtex-II slice contains
logic (MUXF5 and MUXFX multiplexers) that combines
function generators to provide any function of five, six,
seven, or eight inputs. The MUXFX are either MUXF6,
MUXF7 or MUXF8 according to the slice considered in the
CLB. Selected functions up to nine inputs (MUXF5 multi-
plexer) can be implemented in one slice. The MUXFX can
also be a MUXF6, MUXF7, or MUXF8 multiplexers to map
any functions of six, seven, or eight inputs and selected
wide logic functions.
Register/Latch
The storage elements in a Virtex-II slice can be configured
either as edge-triggered D-type flip-flops or as level-sensi-
tive latches. The D input can be directly driven by the X or Y
output via the DX or DY input, or by the slice inputs bypass-
ing the function generators via the BX or BY input. The clock
enable signal (CE) is active High by default. If left uncon-
nected, the clock enable for that storage element defaults to
the active state.
In addition to clock (CK) and clock enable (CE) signals,
each slice has set and reset signals (SR and BY slice
inputs). SR forces the storage element into the state speci-
fied by the attribute SRHIGH or SRLOW. SRHIGH forces a
logic “1” when SR is asserted. SRLOW forces a logic “0”.
When SR is used, a second input (BY) forces the storage
element into the opposite state. The reset condition is pre-
dominant over the set condition. (See Figure 17.)
The initial state after configuration or global initial state is
defined by a separate INIT0 and INIT1 attribute. By default,
setting the SRLOW attribute sets INIT0, and setting the
SRHIGH attribute sets INIT1. For each slice, set and reset
can be set to be synchronous or asynchronous. Virtex-II
devices also have the ability to set INIT0 and INIT1 indepen-
dent of SRHIGH and SRLOW.
The control signals clock (CLK), clock enable (CE) and
set/reset (SR) are common to both storage elements in one
slice. All of the control signals have independent polarity. Any
inverter placed on a control input is automatically absorbed.
Figure 14: Virtex-II CLB Element
Figure 15: Virtex-II Slice Configuration
Slice
X1Y1
Slice
X1Y0
Slice
X0Y1
Slice
X0Y0
Fast
Connects
to neighbors
Switch
Matrix
DS031_32_101600
SHIFT
CIN
COUT
TBUF X0Y1
COUT
CIN
TBUF X0Y0
Register
MUXF5
MUXFx
CY
SRL16
RAM16
LUT
G
Register
Arithmetic Logic
CY
LUT
F
DS031_31_100900
SRL16
RAM16
ORCY
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XC2V6000-4BF957CES | 制造商:Xilinx 功能描述: |
| XC2V6000-4BF957I | 功能描述:IC FPGA VIRTEX-II 957FCBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-II 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC2V6000-4BFG957I | 功能描述:IC FPGA VIRTEX-II 957FCBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-II 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC2V6000-4CS144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-II Platform FPGAs: Complete Data Sheet |
| XC2V6000-4CS144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-II Platform FPGAs: Complete Data Sheet |
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