1. At power-up, VCC" />
參數(shù)資料
型號: XC3030L-8VQ64I
廠商: Xilinx Inc
文件頁數(shù): 17/76頁
文件大小: 0K
描述: IC FPGA I-TEMP 3.3V 64-VQFP
產(chǎn)品變化通告: XC3000(L) Discontinuation 01/Feb/2003
標準包裝: 160
系列: XC3000A/L
LAB/CLB數(shù): 100
RAM 位總計: 22176
輸入/輸出數(shù): 54
門數(shù): 2000
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 64-TQFP
供應商設備封裝: 64-VQFP(10x10)
R
XC3000 Series Field Programmable Gate Arrays
7-26
November 9, 1998 (Version 3.1)
Notes:
1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a
non-monotonically rising VCC may require >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P
after VCC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
High.
3. Master-serial-mode timing is based on slave-mode testing.
Figure 24: Master Serial Mode Programming Switching Characteristics
Serial Data In
CCLK
(Output)
Serial DOUT
(Output)
1
TDSCK
2
TCKDS
n
n + 1
n + 2
n – 3
n – 2
n – 1
n
X3223
Description
Symbol
Min
Max
Units
CCLK
Data In setup
1
TDSCK
60
ns
Data In hold
2
CKDS
0ns
Product Obsolete or Under Obsolescence
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