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參數(shù)資料
| 型號： | XC3090A-7TQ176C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 9/76頁 |
| 文件大小： | 0K |
| 描述： | IC LOGIC GATE ARRAY, 176TQFP |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 320 |
| RAM 位總計： | 64160 |
| 輸入/輸出數(shù)： | 144 |
| 門數(shù)： | 6000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 176-LQFP |
| 供應(yīng)商設(shè)備封裝： | 176-TQFP（24x24） |
| 其它名稱： | Q1151314 XC3090A7TQ176C |
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R
November 9, 1998 (Version 3.1)
7-19
XC3000 Series Field Programmable Gate Arrays
7
Configuration
Initialization Phase
An internal power-on-reset circuit is triggered when power
is applied. When VCC reaches the voltage at which portions
of the FPGA device begin to operate (nominally 2.5 to 3 V),
the programmable I/O output buffers are 3-stated and a
high-impedance pull-up resistor is provided for the user
I/O pins. A time-out delay is initiated to allow the power
supply voltage to stabilize. During this time the power-down
mode is inhibited. The Initialization state time-out (about 11
to 33 ms) is determined by a 14-bit counter driven by a
self-generated internal timer. This nominal 1-MHz timer is
subject to variations with process, temperature and power
supply. As shown in Table 1, five configuration mode
choices are available as determined by the input levels of
three mode pins; M0, M1 and M2.
In Master configuration modes, the device becomes the
source of the Configuration Clock (CCLK). The beginning
of configuration of devices using Peripheral or Slave
modes must be delayed long enough for their initialization
to be completed. An FPGA with mode lines selecting a
Master configuration mode extends its initialization state
using four times the delay (43 to 130 ms) to assure that all
daisy-chained slave devices, which it may be driving, will
be ready even if the master is very fast, and the slave(s)
very slow. Figure 20 shows the state sequences. At the end
of Initialization, the device enters the Clear state where it
clears
the
configuration
memory.
The
active
Low,
open-drain initialization signal INIT indicates when the Ini-
tialization and Clear states are complete. The FPGA tests
for the absence of an external active Low RESET before it
makes a final sample of the mode lines and enters the Con-
figuration state. An external wired-AND of one or more INIT
pins can be used to control configuration by the assertion of
the active-Low RESET of a master mode device or to sig-
nal a processor that the FPGAs are not yet initialized.
If a configuration has begun, a re-assertion of RESET for a
minimum of three internal timer cycles will be recognized
and the FPGA will initiate an abort, returning to the Clear
state to clear the partially loaded configuration memory
words. The FPGA will then resample RESET and the mode
lines before re-entering the Configuration state.
During configuration, the XC3000A, XC3000L, XC3100A,
and XC3100L devices check the bit-stream format for stop
bits in the appropriate positions. Any error terminates the
configuration and pulls INIT Low.
Table 1: Configuration Mode Choices
M0 M1 M2
CCLK
Mode
Data
0
output
Master
Bit Serial
0
1
output
Master
Byte Wide Addr. = 0000 up
010
—
reserved
—
0
1
output
Master
Byte Wide Addr. = FFFF down
1
0
—
reserved
—
1
0
1
output
Peripheral Byte Wide
1
0
—
reserved
—
1
input
Slave
Bit Serial
All User I/O Pins 3-Stated with High Impedance Pull-Up, HDC=High, LDC=Low
Initialization
Power-On
Time Delay
Clear
Configuration
Memory
Test
Mode Pins
Configuration
Program Mode
Start-Up
Operational
Mode
Power Down
No HDC, LDC
or Pull-Up
No
X3399
INIT Output = Low
Clear Is
~ 200 Cycles for the XC3020A—130 to 400
s
~ 250 Cycles for the XC3030A—165 to 500
s
~ 290 Cycles for the XC3042A—195 to 580
s
~ 330 Cycles for the XC3064A—220 to 660
s
~ 375 Cycles for the XC3090A—250 to 750
s
RESET
Active
PWRDWN
Inactive
PWRDWN
Active
Active RESET
Operates on
User Logic
Low on DONE/PROGRAM and RESET
Active RESET
Power-On Delay is
214 Cycles for Non-Master Mode—11 to 33 ms
216 Cycles for Master Mode—43 to 130 ms
Figure 20: A State Diagram of the Configuration Process for Power-up and Reprogram.
Product Obsolete or Under Obsolescence
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3090A-7TQ176I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3090B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| XC3090L | 制造商:XILINX 制造商全稱:XILINX 功能描述:Logic Cell Array Families |
| XC3090L-8PC84C | 功能描述:IC FPGA 3.3V C-TEMP 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC3090L-8PC84I | 功能描述:IC FPGA 3.3V I-TEMP 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
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