- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4176 > XC3164A-3PC84C (Xilinx Inc)IC LOGIC CL ARRAY 6400GAT 84PLCC PDF資料下載
參數(shù)資料
| 型號(hào)： | XC3164A-3PC84C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 44/76頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LOGIC CL ARRAY 6400GAT 84PLCC |
| 產(chǎn)品變化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 224 |
| RAM 位總計(jì)： | 46064 |
| 輸入/輸出數(shù)： | 70 |
| 門數(shù)： | 4500 |
| 電源電壓： | 4.25 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC |
| 其它名稱： | 122-1045 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)當(dāng)前第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)
R
November 9, 1998 (Version 3.1)
7-51
XC3000 Series Field Programmable Gate Arrays
7
XC3000L IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configured as a user input.
Speed Grade
-8
Description
Symbol
Min
Max
Units
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
3
4
TPID
TPTG
TIKRI
5.0
24.0
6.0
ns
Set-up Time (Input)
Pad to Clock (IK) set-up time
1
TPICK
22.0
ns
Propagation Delays (Output)
Clock (OK) to Pad
(fast)
same
(slew rate limited)
Output (O) to Pad
(fast)
same
(slew-rate limited)
3-state to Pad begin hi-Z
(fast)
same
(slew-rate limited)
3-state to Pad active and valid
(fast)
same
(slew -rate limited)
7
10
9
8
TOKPO
TOPF
TOPS
TTSHZ
TTSON
12.0
28.0
9.0
25.0
12.0
28.0
16.0
32.0
ns
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
5
6
TOOK
TOKO
12.0
0
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12
TIOH
TIOL
FCLK
5.0
80.0
ns
MHz
Global Reset Delays (based on XC3042L)
RESET Pad to Registered In
(Q)
RESET Pad to output pad
(fast)
(slew-rate limited)
13
15
TRRI
TRPO
25.0
35.0
51.0
ns
Product Obsolete or Under Obsolescence
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AMC36DRYN-S13 | CONN EDGECARD 72POS .100 EXTEND |
| XC3142A-3PQ100C | IC LOGIC CL ARRAY 4200GAT 100PQF |
| AMC36DRYH-S13 | CONN EDGECARD 72POS .100 EXTEND |
| XC3130A-3PQ100C | IC LOGIC CL ARRAY 3000GAT 100PQF |
| XC3130A-3PC84C | IC LOGIC CL ARRAY 3000GAT 84PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3164A-3PC84I | 制造商:Xilinx 功能描述: |
| XC3164A-3PQ160C | 制造商:Xilinx 功能描述: |
| XC3164A-3PQ160I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3164A-3TQ144C | 功能描述:IC FPGA 224 CLB'S 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC3164A-3TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。