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| 型號(hào)： | XC3S1200E-5FGG320C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 153/227頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN-3E 1200K 320FBGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 系列： | Spartan®-3E |
| LAB/CLB數(shù)： | 2168 |
| 邏輯元件/單元數(shù)： | 19512 |
| RAM 位總計(jì)： | 516096 |
| 輸入/輸出數(shù)： | 250 |
| 門數(shù)： | 1200000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 320-BGA |
| 供應(yīng)商設(shè)備封裝： | 320-FBGA（19x19） |
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
31
The MULT_AND is useful for small multipliers. Larger
multipliers can be built using the dedicated 18x18 multiplier
blocks (see Dedicated Multipliers).
Storage Elements
The storage element, which is programmable as either a
D-type flip-flop or a level-sensitive transparent latch,
provides a means for synchronizing data to a clock signal,
among other uses. The storage elements in the top and
bottom portions of the slice are called FFY and FFX,
respectively. FFY has a fixed multiplexer on the D input
selecting either the combinatorial output Y or the bypass
signal BY. FFX selects between the combinatorial output X
or the bypass signal BX.
The functionality of a slice storage element is identical to
that described earlier for the I/O storage elements. All
signals have programmable polarity; the default active-High
function is described.
The control inputs R, S, CE, and C are all shared between
the two flip-flops in a slice.
X-Ref Target - Figure 24
Figure 24: Using the MULT_AND for Multiplication in
Carry Logic
Bn+1
Am
Bn
Am+1
Pm+1
CIN
DS312-2_39_021305
COUT
LUT
MULT_AND
Table 15: Storage Element Signals
Signal
Description
D
Input. For a flip-flop data on the D input is loaded when R and S (or CLR and PRE) are Low and CE is High during the
Low-to-High clock transition. For a latch, Q reflects the D input while the gate (G) input and gate enable (GE) are High and R
and S (or CLR and PRE) are Low. The data on the D input during the High-to-Low gate transition is stored in the latch. The
data on the Q output of the latch remains unchanged as long as G or GE remains Low.
Q
Output. Toggles after the Low-to-High clock transition for a flip-flop and immediately for a latch.
C
Clock for edge-triggered flip-flops.
G
Gate for level-sensitive latches.
CE
Clock Enable for flip-flops.
GE
Gate Enable for latches.
S
Synchronous Set (Q = High). When the S input is High and R is Low, the flip-flop is set, output High, during the Low-to-High
clock (C) transition. A latch output is immediately set, output High.
R
Synchronous Reset (Q = Low); has precedence over Set.
PRE
Asynchronous Preset (Q = High). When the PRE input is High and CLR is Low, the flip-flop is set, output High, during the
Low-to-High clock (C) transition. A latch output is immediately set, output High.
CLR
Asynchronous Clear (Q = Low); has precedence over Preset to reset Q output Low
SR
CLB input for R, S, CLR, or PRE
REV
CLB input for opposite of SR. Must be asynchronous or synchronous to match SR.
X-Ref Target - Figure 25
Figure 25: FD Flip-Flop Component with Synchronous
Reset, Set, and Clock Enable
FDRSE
DQ
CE
C
R
S
DS312-2_40_021305
Table 16: FD Flip-Flop Functionality with Synchronous
Reset, Set, and Clock Enable
Inputs
Outputs
RS
CE
D
C
Q
1
X
↑
0
01
X
↑
1
00
0
X
No Change
00
11
↑
1
00
10
↑
0
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| XC3S1200E-4FGG320I | IC FPGA SPARTAN-3E 1200K 320FBGA |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1200E-5FGG320I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S1200E-5FGG400C | 功能描述:IC FPGA SPARTAN-3E 1200K 400FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC3S1200E-5FGG400I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S1200E-5FGG484C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S1200E-5FGG484I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
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