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| 型號(hào)： | XC3S1200E-5FGG320C |
| 廠(chǎng)商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 46/227頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA SPARTAN-3E 1200K 320FBGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 系列： | Spartan®-3E |
| LAB/CLB數(shù)： | 2168 |
| 邏輯元件/單元數(shù)： | 19512 |
| RAM 位總計(jì)： | 516096 |
| 輸入/輸出數(shù)： | 250 |
| 門(mén)數(shù)： | 1200000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 320-BGA |
| 供應(yīng)商設(shè)備封裝： | 320-FBGA（19x19） |
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
14
Double-Data-Rate Transmission
Double-Data-Rate (DDR) transmission describes the
technique of synchronizing signals to both the rising and
falling edges of the clock signal. Spartan-3E devices use
register pairs in all three IOB paths to perform DDR
operations.
The pair of storage elements on the IOB’s Output path
(OFF1 and OFF2), used as registers, combine with a
special multiplexer to form a DDR D-type flip-flop (ODDR2).
This primitive permits DDR transmission where output data
bits are synchronized to both the rising and falling edges of
a clock. DDR operation requires two clock signals (usually
50% duty cycle), one the inverted form of the other. These
signals trigger the two registers in alternating fashion, as
shown in Figure 7. The Digital Clock Manager (DCM)
generates the two clock signals by mirroring an incoming
signal, and then shifting it 180 degrees. This approach
ensures minimal skew between the two signals.
Alternatively, the inverter inside the IOB can be used to
invert the clock signal, thus only using one clock line and
both rising and falling edges of that clock line as the two
clocks for the DDR flip-flops.
The storage-element pair on the Three-State path (TFF1
and TFF2) also can be combined with a local multiplexer to
form a DDR primitive. This permits synchronizing the output
enable to both the rising and falling edges of a clock. This
DDR operation is realized in the same way as for the output
path.
The storage-element pair on the input path (IFF1 and IFF2)
allows an I/O to receive a DDR signal. An incoming DDR
clock signal triggers one register, and the inverted clock
signal triggers the other register. The registers take turns
capturing bits of the incoming DDR data signal. The
primitive to allow this functionality is called IDDR2.
Aside from high bandwidth data transfers, DDR outputs also
can be used to reproduce, or mirror, a clock signal on the
output. This approach is used to transmit clock and data
signals together (source synchronously). A similar
approach is used to reproduce a clock signal at multiple
outputs. The advantage for both approaches is that skew
across the outputs is minimal.
Register Cascade Feature
In the Spartan-3E family, one of the IOBs in a differential
pair can cascade its input storage elements with those in
the other IOB as part of a differential pair. This is intended to
make DDR operation at high speed much simpler to
implement. The new DDR connections that are available
are shown in Figure 5 (dashed lines), and are only available
for routing between IOBs and are not accessible to the
FPGA fabric. Note that this feature is only available when
using the differential I/O standards LVDS, RSDS, and
MINI_LVDS.
IDDR2
As a DDR input pair, the master IOB registers incoming
data on the rising edge of ICLK1 (= D1) and the rising edge
of ICLK2 (= D2), which is typically the same as the falling
edge of ICLK1. This data is then transferred into the FPGA
fabric. At some point, both signals must be brought into the
same clock domain, typically ICLK1. This can be difficult at
high frequencies because the available time is only one half
of a clock cycle assuming a 50% duty cycle. See Figure 8
for a graphical illustration of this function.
X-Ref Target - Figure 7
Figure 7: Two Methods for Clocking the DDR Register
DS312-2_20_021105
D1
CLK1
DDR MUX
DCM
Q1
FDDR
D2
CLK2
Q2
180 0
Q
D1
CLK1
DDR MUX
DCM
Q1
FDDR
D2
CLK2
Q2
0
Q
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 24LC32AT-E/MC | IC EEPROM 32KBIT 400KHZ 8DFN |
| 25LC040AT-I/MC | IC EEPROM 4KBIT 10MHZ 8DFN |
| 25LC020AT-E/ST | IC EEPROM 2KBIT 10MHZ 8TSSOP |
| XC3S1200E-4FGG320I | IC FPGA SPARTAN-3E 1200K 320FBGA |
| 25LC020AT-E/MS | IC EEPROM 2KBIT 10MHZ 8MSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1200E-5FGG320I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S1200E-5FGG400C | 功能描述:IC FPGA SPARTAN-3E 1200K 400FBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門(mén)數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC3S1200E-5FGG400I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S1200E-5FGG484C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S1200E-5FGG484I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3E FPGA Family |
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