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| 型號(hào)： | XC3S400-4TQG144C |
| 廠(chǎng)商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 2/272頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 400K STD 144TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 896 |
| 邏輯元件/單元數(shù)： | 8064 |
| RAM 位總計(jì)： | 294912 |
| 輸入/輸出數(shù)： | 97 |
| 門(mén)數(shù)： | 400000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 其它名稱(chēng)： | 122-1717 XC3S400-4TQG144C-ND |
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Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013
Product Specification
10
IOBs
For additional information, refer to the chapter entitled “Using I/O Resources” in UG331: Spartan-3 Generation FPGA User
Guide.
IOB Overview
The Input/Output Block (IOB) provides a programmable, bidirectional interface between an I/O pin and the FPGA’s internal
logic.
A simplified diagram of the IOB’s internal structure appears in Figure 7. There are three main signal paths within the IOB: the
output path, input path, and 3-state path. Each path has its own pair of storage elements that can act as either registers or
latches. For more information, see the Storage Element Functions section. The three main signal paths are as follows:
The input path carries data from the pad, which is bonded to a package pin, through an optional programmable delay
element directly to the I line. There are alternate routes through a pair of storage elements to the IQ1 and IQ2 lines.
The IOB outputs I, IQ1, and IQ2 all lead to the FPGA’s internal logic. The delay element can be set to ensure a hold
time of zero.
The output path, starting with the O1 and O2 lines, carries data from the FPGA’s internal logic through a multiplexer
and then a three-state driver to the IOB pad. In addition to this direct path, the multiplexer provides the option to insert
a pair of storage elements.
The 3-state path determines when the output driver is high impedance. The T1 and T2 lines carry data from the
FPGA’s internal logic through a multiplexer to the output driver. In addition to this direct path, the multiplexer provides
the option to insert a pair of storage elements. When the T1 or T2 lines are asserted High, the output driver is
high-impedance (floating, hi-Z). The output driver is active-Low enabled.
All signal paths entering the IOB, including those associated with the storage elements, have an inverter option. Any
inverter placed on these paths is automatically absorbed into the IOB.
Storage Element Functions
There are three pairs of storage elements in each IOB, one pair for each of the three paths. It is possible to configure each
of these storage elements as an edge-triggered D-type flip-flop (FD) or a level-sensitive latch (LD).
The storage-element-pair on either the Output path or the Three-State path can be used together with a special multiplexer
to produce Double-Data-Rate (DDR) transmission. This is accomplished by taking data synchronized to the clock signal’s
rising edge and converting them to bits synchronized on both the rising and the falling edge. The combination of two
registers and a multiplexer is referred to as a Double-Data-Rate D-type flip-flop (FDDR). See Double-Data-Rate
Transmission, page 12 for more information.
The signal paths associated with the storage element are described in Table 5.
Table 5: Storage Element Signal Description
Storage
Element
Signal
Description
Function
D
Data input
Data at this input is stored on the active edge of CK enabled by CE. For latch operation when the
input is enabled, data passes directly to the output Q.
Q
Data output
The data on this output reflects the state of the storage element. For operation as a latch in
transparent mode, Q will mirror the data at D.
CK
Clock input
A signal’s active edge on this input with CE asserted, loads data into the storage element.
CE
Clock Enable input
When asserted, this input enables CK. If not connected, CE defaults to the asserted state.
SR
Set/Reset
Forces storage element into the state specified by the SRHIGH/SRLOW attributes. The
SYNC/ASYNC attribute setting determines if the SR input is synchronized to the clock or not.
REV
Reverse
Used together with SR. Forces storage element into the state opposite from what SR does.
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| XC3S400-4TQG144I | 功能描述:SPARTAN-3A FPGA 400K STD 144TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Spartan®-3 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門(mén)數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC3S400-4TQG14C | 制造商:Xilinx 功能描述: |
| XC3S400-4VQ100C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA |
| XC3S400-4VQ100I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA |
| XC3S400-4VQG100C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
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