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參數(shù)資料
| 型號(hào)： | XC3S400-4TQG144C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 228/272頁(yè) |
| 文件大小： | 0K |
| 描述： | SPARTAN-3A FPGA 400K STD 144TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 896 |
| 邏輯元件/單元數(shù)： | 8064 |
| RAM 位總計(jì)： | 294912 |
| 輸入/輸出數(shù)： | 97 |
| 門數(shù)： | 400000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 其它名稱： | 122-1717 XC3S400-4TQG144C-ND |
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Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013
Product Specification
59
IIK
Input clamp current per I/O pin
–0.5 V
< VIN < (VCCO + 0.5 V)
–
±100
mA
VESD
Electrostatic Discharge Voltage pins relative
to GND
Human body model
–
±2000
V
Charged device model
–±500
V
Machine model
–±200
V
TJ
Junction temperature
–125
°C
TSOL
Soldering temperature(4)
–220
°C
TSTG
Storage temperature
–65
150
°C
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not
implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.
2.
All User I/O and Dual-Purpose pins (DIN/D0, D1–D7, CS_B, RDWR_B, BUSY/DOUT, and INIT_B) draw power from the VCCO power rail of
the associated bank. Keeping VIN within 500 mV of the associated VCCO rails or ground rail ensures that the internal diode junctions that
exist between each of these pins and the VCCO and GND rails do not turn on. Table 32 specifies the VCCO range used to determine the max
limit. Input voltages outside the –0.5V to VCCO+0.5V voltage range are permissible provided that the IIK input clamp diode rating is met and
no more than 100 pins exceed the range simultaneously. Prolonged exposure to such current may compromise device reliability. A sustained
current of 10 mA will not compromise device reliability. See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing
Single-Ended Signals to User I/O Pins on Spartan-3 Generation FPGAs for more details. The VIN limits apply to both the DC and AC
components of signals. Simple application solutions are available that show how to handle overshoot/undershoot as well as achieve PCI
compliance. Refer to the following application notes: XAPP457, Powering and Configuring Spartan-3 Generation FPGAs in Compliant PCI
Applications and XAPP659, Virtex-II Pro / Virtex-II Pro X 3.3V I/O Design Guidelines.
3.
All Dedicated pins (M0–M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail (2.5V).
Meeting the VIN max limit ensures that the internal diode junctions that exist between each of these pins and the VCCAUX rail do not turn on.
Table 32 specifies the VCCAUX range used to determine the max limit. When VCCAUX is at its maximum recommended operating level
(2.625V), VIN max < 3.125V. As long as the VIN max specification is met, oxide stress is not possible. For information concerning the use of
3.3V signals, see the 3.3V-Tolerant Configuration Interface, page 47. See also XAPP459.
4.
For soldering guidelines, see UG112, Device Packaging and Thermal Characteristics and XAPP427, Implementation and Solder Reflow
Guidelines for Pb-Free Packages.
Table 29: Supply Voltage Thresholds for Power-On Reset
Symbol
Description
Min
Max
Units
VCCINTT
Threshold for the VCCINT supply
0.4
1.0
V
VCCAUXT
Threshold for the VCCAUX supply
0.8
2.0
V
VCCO4T
Threshold for the VCCO Bank 4 supply
0.4
1.0
V
Notes:
1.
VCCINT, VCCAUX, and VCCO supplies may be applied in any order. When applying VCCINT power before VCCAUX power, the FPGA may draw
a surplus current in addition to the quiescent current levels specified in Table 34. Applying VCCAUX eliminates the surplus current. The FPGA
does not use any of the surplus current for the power-on process. For this power sequence, make sure that regulators with foldback features
will not shut down inadvertently.
2.
To ensure successful power-on, VCCINT, VCCO Bank 4, and VCCAUX supplies must rise through their respective threshold-voltage ranges
with no dips at any point.
3.
If a brown-out condition occurs where VCCAUX or VCCINT drops below the retention voltage indicated in Table 31, then VCCAUX or VCCINT
must drop below the minimum power-on reset voltage in order to clear out the device configuration content.
Table 28: Absolute Maximum Ratings (Cont’d)
Symbol
Description
Conditions
Min
Max
Units
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| XC3S400-4TQG144I | 功能描述:SPARTAN-3A FPGA 400K STD 144TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC3S400-4TQG14C | 制造商:Xilinx 功能描述: |
| XC3S400-4VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S400-4VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S400-4VQG100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
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