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參數(shù)資料
| 型號(hào)： | XC4000XLASERIES |
| 廠(chǎng)商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列 |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大?。?/td> | 142K |
| 代理商： | XC4000XLASERIES |
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DS015 (v1.3) October 18, 1999 - Product Specication
6-159
XC4000XLA/XV Field Programmable Gate Arrays
6
Three-State Register
XC4000XLA/XV devices incorporate an optional register
controlling the three-state enable in the IOBs.The use of
the three-state control register can signicantly improve
output enable and disable time.
FastCLK Clock Buffers
The XLA/XV devices incorporate FastCLK clock buffers.
Two FastCLK buffers are available on each of the right and
left edges of the die. Each FastCLK buffer can provide a
fast clock signal (typically < 1.5 ns clock delay) to all the
IOBs within the IOB octant containing the buffer. The Fast-
CLK buffers can be instantiated by use of the BUFFCLK
symbols. (In addition to FastCLK buffers, the Global Early
BUFGE clock buffers #1, #2, #5, and #6 can also provide
fast clock signals (typically < 1.5 ns clock delay) to IOBs on
the top and bottom of the die.
XLA/XV Power Requirements
XC4000XLA devices require 40% less power per CLB than
equivalent XL devices. XC4000XV devices require 42%
less power per CLB than equivalent XLA devices and 65%
less power than XL devices The representative K-Factor for
the following families can be found in Table 2. The K-Factor
predicts device current for typical user designs and is
based on lling the FPGA with active 16-Bit counters and
measuring the device current at 1 MHz. This technique is
described in XBRF14 “A Simple Method of Estimating
Power in XC4000XL/EX/E FPGAs”. To predict device
power (P) using the K-Factor use the following formula:
P=V*K*N*F; where:
P= Device Power
V= Power supply voltage
K= the Device K-Factor
N = number of active registers
F = Frequency in MHz
XLA/XV Logic Performance
XC4000XLA/XV devices feature 30% faster device speed
than XL devices, and consistent performance is achieved
across all family members. Table 3 illustrates the perfor-
mance of the XLA devices. For details regarding the imple-
mentation of these benchmarks refer to XBRF15 “Speed
Metrics for High Performance FPGAs”.
Table 2: K-Factor and Relative Power.
FPGA Family
K-Factor
Power
Relative To
XL
Power
Relative To
XLA
XC4000XL
28
1.00
1.65
XC4000XLA
17
0.60
1.00
XC4000XV
13
0.35
0.58
Table 3: XLA/XV Estimated Benchmark Performance
Register - Register
Benchmarks
Size
Maximum
Frequency
Adder
8-Bit
172 MHz
16-Bit
144 MHz
32-Bit
108 MHz
2 Cascaded Adders
16-Bit
94 MHz
4 Cascaded Adders
16-Bit
57 MHz
Cascaded 4LUTs
1 Level
314 MHz
2 Level
193 MHz
4 Level
108 MHz
6 Level
75 MHz
Interconnect
(Manhattan Distance)
1 CLBs
325 MHz
4 CLBs
260 MHz
16 CLBs
185 MHz
64 CLBs
108 MHz
128 CLBs
81 MHz
Dual Port RAM
(Pipelined)
8-Bits by 16
172 MHz
8-Bits by 256
172 MHz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4000XSERIES | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Programmable Gate Arrays |
| XC4000XV | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:XC4000XLA/XV Field Programmable Gate Arrays |
| XC4000XVSERIES | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays |
| XC4002 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述: |
| XC4002A | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Logic Cell Array Families |
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