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  • 參數(shù)資料
    型號: XC4013XL-3HT176C
    廠商: Xilinx Inc
    文件頁數(shù): 68/68頁
    文件大?。?/td> 0K
    描述: IC FPGA C 3.3V 3SPD 176HTQFP
    產(chǎn)品變化通告: XC4000(XL,XLA,E) Discontinuation 15/Nov/2004
    標準包裝: 40
    系列: XC4000E/X
    LAB/CLB數(shù): 576
    邏輯元件/單元數(shù): 1368
    RAM 位總計: 18432
    輸入/輸出數(shù): 145
    門數(shù): 13000
    電源電壓: 3 V ~ 3.6 V
    安裝類型: 表面貼裝
    工作溫度: 0°C ~ 85°C
    封裝/外殼: 176-LQFP 裸露焊盤
    供應商設(shè)備封裝: 176-TQFP(24x24)
    R
    May 14, 1999 (Version 1.6)
    6-13
    XC4000E and XC4000X Series Field Programmable Gate Arrays
    6
    tions of the CLB, with the exception of the redenition of the
    control signals. In 16x2 and 16x1 modes, the H’ function
    generator can be used to implement Boolean functions of
    F’, G’, and D1, and the D ip-ops can latch the F’, G’, H’, or
    D0 signals.
    Single-Port Edge-Triggered Mode
    Edge-triggered
    (synchronous)
    RAM
    simplies
    timing
    requirements. XC4000 Series edge-triggered RAM timing
    operates like writing to a data register. Data and address
    are presented. The register is enabled for writing by a logic
    High on the write enable input, WE. Then a rising or falling
    clock edge loads the data into the register, as shown in
    Complex timing relationships between address, data, and
    write enable signals are not required, and the external write
    enable pulse becomes a simple clock enable. The active
    edge of WCLK latches the address, input data, and WE sig-
    nals. An internal write pulse is generated that performs the
    write. See Figure 4 and Figure 5 for block diagrams of a
    CLB congured as 16x2 and 32x1 edge-triggered, sin-
    gle-port RAM.
    The relationships between CLB pins and RAM inputs and
    outputs for single-port, edge-triggered mode are shown in
    The Write Clock input (WCLK) can be congured as active
    on either the rising edge (default) or the falling edge. It uses
    the same CLB pin (K) used to clock the CLB ip-ops, but it
    can be independently inverted. Consequently, the RAM
    output can optionally be registered within the same CLB
    either by the same clock edge as the RAM, or by the oppo-
    site edge of this clock. The sense of WCLK applies to both
    function generators in the CLB when both are congured
    as RAM.
    The WE pin is active-High and is not invertible within the
    CLB.
    Note: The pulse following the active edge of WCLK (TWPS
    in Figure 3) must be less than one millisecond wide. For
    most applications, this requirement is not overly restrictive;
    however, it must not be forgotten. Stopping WCLK at this
    point in the write cycle could result in excessive current and
    even damage to the larger devices if many CLBs are con-
    gured as edge-triggered RAM.
    X6461
    WCLK (K)
    WE
    ADDRESS
    DATA IN
    DATA OUT
    OLD
    NEW
    T
    DSS
    T
    DHS
    T
    ASS
    T
    AHS
    T
    WSS
    T
    WPS
    T
    WHS
    T
    WOS
    T
    ILO
    T
    ILO
    Figure 3:
    Edge-Triggered RAM Write Timing
    Table 5: Single-Port Edge-Triggered RAM Signals
    RAM Signal
    CLB Pin
    Function
    D
    D0 or D1 (16x2,
    16x1), D0 (32x1)
    Data In
    A[3:0]
    F1-F4 or G1-G4
    Address
    A[4]
    D1 (32x1)
    Address
    WE
    Write Enable
    WCLK
    K
    Clock
    SPO
    (Data Out)
    F’ or G’
    Single Port Out
    (Data Out)
    Product Obsolete or Under Obsolescence
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