參數(shù)資料
型號(hào)： XC4036XL-2BG352I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 21/68頁(yè)
文件大?。?/td> 0K
描述： IC FPGA I-TEMP 3.3V 2SPD 352MBGA
產(chǎn)品變化通告： XC4000(XL,XLA,E) Discontinuation 15/Nov/2004
標(biāo)準(zhǔn)包裝： 24
系列： XC4000E/X
LAB/CLB數(shù)： 1296
邏輯元件/單元數(shù)： 3078
RAM 位總計(jì)： 41472
輸入/輸出數(shù)： 288
門(mén)數(shù)： 36000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 352-LBGA，金屬
供應(yīng)商設(shè)備封裝： 352-MBGA（35x35）
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-32
May 14, 1999 (Version 1.6)
circuit prevents undened oating levels. However, it is
overridden by any driver, even a pull-up resistor.
Each XC4000E longline has a programmable splitter switch
at its center, as does each XC4000X longline driven by
TBUFs. This switch can separate the line into two indepen-
dent routing channels, each running half the width or height
of the array.
Each XC4000X longline not driven by TBUFs has a buff-
ered programmable splitter switch at the 1/4, 1/2, and 3/4
points of the array. Due to the buffering, XC4000X longline
performance does not deteriorate with the larger array
sizes. If the longline is split, the resulting partial longlines
are independent.
Routing connectivity of the longlines is shown in Figure 27
Direct Interconnect (XC4000X only)
The XC4000X offers two direct, efcient and fast connec-
tions between adjacent CLBs. These nets facilitate a data
ow from the left to the right side of the device, or from the
top to the bottom, as shown in Figure 30. Signals routed on
the direct interconnect exhibit minimum interconnect prop-
agation delay and use no general routing resources.
The direct interconnect is also present between CLBs and
adjacent IOBs. Each IOB on the left and top device edges
has a direct path to the nearest CLB. Each CLB on the right
and bottom edges of the array has a direct path to the near-
est two IOBs, since there are two IOBs for each row or col-
umn of CLBs.
The place and route software uses direct interconnect
whenever possible, to maximize routing resources and min-
imize interconnect delays.
I/O Routing
XC4000 Series devices have additional routing around the
IOB ring. This routing is called a VersaRing. The VersaRing
facilitates pin-swapping and redesign without affecting
board layout. Included are eight double-length lines span-
ning two CLBs (four IOBs), and four longlines. Global lines
and Wide Edge Decoder lines are provided. XC4000X
devices also include eight octal lines.
A high-level diagram of the VersaRing is shown in
Figure 31. The shaded arrows represent routing present
only in XC4000X devices.
Figure 33 on page 34 is a detailed diagram of the XC4000E
and XC4000X VersaRing. The area shown includes two
IOBs. There are two IOBs per CLB row or column, there-
fore this diagram corresponds to the CLB routing diagram
shown in Figure 27 on page 30. The shaded areas repre-
sent routing and routing connections present only in
XC4000X devices.
Octal I/O Routing (XC4000X only)
Between the XC4000X CLB array and the pad ring, eight
interconnect tracks provide for versatility in pin assignment
and xed pinout exibility. (See Figure 32 on page 33.)
These routing tracks are called octals, because they can be
broken every eight CLBs (sixteen IOBs) by a programma-
ble buffer that also functions as a splitter switch. The buffers
are staggered, so each line goes through a buffer at every
eighth CLB location around the device edge.
The octal lines bend around the corners of the device. The
lines cross at the corners in such a way that the segment
most recently buffered before the turn has the farthest dis-
tance to travel before the next buffer, as shown in
CLB
IOB
X6603
IOB
CLB
~~
~ ~
Figure 30: XC4000X Direct Interconnect
Product Obsolete or Under Obsolescence
相關(guān)PDF資料
PDF描述
XC4036XL-2BG352C IC FPGA C-TEMP 3.3V 2SPD 352MBGA
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