參數(shù)資料
型號: XC4VFX12-11SFG363I
廠商: Xilinx Inc
文件頁數(shù): 7/58頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-4 FX 12K 363FCBGA
標(biāo)準(zhǔn)包裝: 90
系列: Virtex®-4 FX
LAB/CLB數(shù): 1368
邏輯元件/單元數(shù): 12312
RAM 位總計(jì): 663552
輸入/輸出數(shù): 240
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 363-FBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 363-FCBGA(17x17)
配用: HW-V4-ML403-UNI-G-ND - EVALUATION PLATFORM VIRTEX-4
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
15
Table 19: PowerPC 405 Data-Side On-Chip Memory Switching Characteristics
Description
Symbol
Speed Grade
Units
-12
-11
-10
Setup and Hold Relative to Clock (BRAMDSOCMCLK)
Data-Side On-Chip Memory data bus inputs
TPPCDCK_DSOCMRDDB
TPPCCKD_DSOCMRDDB
0.60
0.20
0.65
0.20
0.74
0.23
ns, Min
Clock to Out
Data-Side On-Chip Memory control outputs
TPPCCKO_BRAMBWR
2.07
2.30
2.65
ns, Max
Data-Side On-Chip Memory address bus outputs
TPPCCKO_BRAMABUS
2.07
2.30
2.65
ns, Max
Data-Side On-Chip Memory data bus outputs
TPPCCKO_IBRAMWRDBUS01
1.61
1.79
2.06
ns, Max
Table 20: PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics
Description
Symbol
Speed Grade
Units
-12
-11
-10
Setup and Hold Relative to Clock (BRAMISOCMCLK)
Instruction-Side On-Chip Memory data bus inputs
TPPCDCK_ISOCMRDDB
TPPCCKD_ISOCMRDDB
0.74
0.20
0.82
0.20
0.94
0.23
ns, Min
Clock to Out
Instruction-Side On-Chip Memory control outputs
TPPCCKO_IBRAMEN
3.04
3.37
3.88
ns, Max
Instruction-Side On-Chip Memory address bus outputs
TPPCCKO_IBRAMRDABUS
1.67
1.85
2.13
ns, Max
Instruction-Side On-Chip Memory data bus outputs
TPPCCKO_IBRAMWRDBUS
1.67
1.86
2.14
ns, Max
Table 21: Processor Block DCR Bus Switching Characteristics
Description
Symbol
Speed Grade
Units
-12
-11
-10
Setup and Hold Relative to Clock (CPMDCRCLOCK)
Device Control Register Bus control inputs
TPPCDCK_EXDCRACK
TPPCCKD_EXDCRACK
0.12
0.15
0.13
0.17
0.15
0.19
ns, Min
Device Control Register Bus data inputs
TPPCDCK_EXDCRDBUSI
TPPCCKD_EXDCRDBUSI
0.57
0.16
0.57
0.16
1.02
0.27
ns, Min
Clock to Out
Device Control Register Bus control outputs
TPPCCKO_EXDCRRD
1.20
1.35
1.54
ns, Max
Device Control Register Bus address bus outputs
TPPCCKO_EXDCRABUS
1.28
1.45
1.66
ns, Max
Device Control Register Bus data bus outputs
TPPCCKO_EXDCRDBUSO
1.31
1.45
1.67
ns, Max
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