參數(shù)資料
型號： XC4VLX25-10SFG363C
廠商： Xilinx Inc
文件頁數(shù)： 17/58頁
文件大小： 0K
描述： IC FPGA VIRTEX-4 24K 363-FCBGA
標準包裝： 90
系列： Virtex®-4 LX
LAB/CLB數(shù)： 2688
邏輯元件/單元數(shù)： 24192
RAM 位總計： 1327104
輸入/輸出數(shù)： 240
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 363-FBGA，F(xiàn)CBGA
供應商設(shè)備封裝： 363-FCBGA（17x17）
配用： 807-1004-ND - DAUGHTER CARD WITH VIRTEX-4
122-1523-ND - EVALUATION PLATFORM VIRTEX-4
其它名稱： 122-1489
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
24
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4 inches
of FR4 microstrip trace. Standard termination was used for
all testing. The propagation delay of the 4 inch trace is char-
acterized separately and subtracted from the final measure-
ment, and is therefore not included in the generalized test
setup shown in Figure 4.
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it. Parame-
ters VREF, RREF, CREF, and VMEAS fully describe the test
conditions for each I/O standard. The most accurate predic-
tion of propagation delay in any given application can be
obtained through IBIS simulation, using the following
method:
1.
Simulate the output driver of choice into the generalized
test setup, using values from Table 31.
2.
Record the time to VMEAS.
3.
Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
4.
Record the time to VMEAS.
5.
Compare the results of steps 2 and 4. The increase or
decrease in delay yields the actual worst-case
propagation delay (clock-to-input) of the PCB trace.
Figure 4: Generalized Test Setup
VREF
RREF
VMEAS
(voltage level when taking
delay measurement)
CREF
(probe capacitance)
FPGA Output
DS302_05_031708
Table 31: Output Delay Measurement Methodology
Description
I/O Standard
Attribute
RREF
(
Ω)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVTTL (all)
1M
0
1.4
0
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS33
1M
0
1.65
0
LVCMOS, 2.5V
LVCMOS25
1M
0
1.25
0
LVCMOS, 1.8V
LVCMOS18
1M
0
0.9
0
LVCMOS, 1.5V
LVCMOS15
1M
0
0.75
0
LVCMOS, 1.2V
LVCMOS12
1M
0
0.75
0
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI33_3 (rising edge)
25
10(2)
0.94
0
PCI33_3 (falling edge)
25
10(2)
2.03
3.3
PCI, 66 MHz, 3.3V
PCI66_3 (rising edge)
25
10(2)
0.94
0
PCI66_3 (falling edge)
25
10(2)
2.03
3.3
PCI-X, 133 MHz, 3.3V
PCIX (rising edge)
25
10(3)
0.94
PCIX (falling edge
25
10(3)
2.03
3.3
GTL (Gunning Transceiver Logic)
GTL
25
0
0.8
1.2
GTL Plus
GTLP
25
0
1.0
1.5
HSTL (High-Speed Transceiver Logic), Class I
HSTL_I
50
0
VREF
0.75
HSTL, Class II
HSTL_II
25
0
VREF
0.75
HSTL, Class III
HSTL_III
50
0
0.9
1.5
HSTL, Class IV
HSTL_IV
25
0
0.9
1.5
HSTL, Class I, 1.8V
HSTL_I_18
50
0
VREF
0.9
HSTL, Class II, 1.8V
HSTL_II_18
25
0
VREF
0.9
HSTL, Class III, 1.8V
HSTL_III_18
50
0
1.1
1.8
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