參數(shù)資料
型號: XC4VSX35-10FFG668C
廠商: Xilinx Inc
文件頁數(shù): 30/58頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-4 35K 668-FCBGA
標準包裝: 1
系列: Virtex®-4 SX
LAB/CLB數(shù): 3840
邏輯元件/單元數(shù): 34560
RAM 位總計: 3538944
輸入/輸出數(shù): 448
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 668-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 668-FCBGA
配用: HW-V4-ML402-UNI-G-ND - EVALUATION PLATFORM VIRTEX-4
807-1005-ND - DAUGHTER CARD WITH VIRTEX-4
HW-AFX-FF668-400-ND - BOARD DEV VIRTEX 4 FF668
其它名稱: 122-1498
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
36
Configuration Switching Characteristics
Table 43: Configuration Switching Characteristics
Symbol
Description
Speed Grade
Units
-12
-11
-10
Power-up Timing Characteristics
TCONFIG(1,2)
Maximum time to configure device after
VCCINT has been applied.
10
minutes
TPL
Program Latency
0.5
s/frame,
Max
TPOR
Power-on-Reset
TPL +10 TPL +10 TPL +10
ms, Max
TICCK
CCLK (output) delay
500
ns, Min
TPROGRAM
Program Pulse Width
300
ns, Min
Master/Slave Serial Mode Programming Switching
TDCC / TCCD
DIN Setup/Hold, slave mode
0.5
1.0
0.5
1.0
0.5
1.0
ns, Min
TDSCK / TSCKD
DIN Setup/Hold, master mode
0.5
1.0
0.5
1.0
0.5
1.0
ns, Min
TCCO
DOUT
7.5
ns, Max
TCCH
High Time
2.0
ns, Min
TCCL
Low Time
2.0
ns, Min
FCC_SERIAL
Maximum Frequency, master mode with
respect to nominal CCLK.
100
MHz, Max
FMAX_SLAVE / FMAX_ICAP
Maximum Frequency, slave mode external
CCLK
100
MHz, Max
FMCCTOL
Frequency Tolerance, master mode with
respect to nominal CCLK.
±50
%
SelectMAP Mode Programming Switching
TSMDCC / TSMCCD
SelectMAP Data Setup/Hold
2.0
0.0
2.0
0.0
2.0
0.0
ns, Min
TSMCSCC / TSMCCCS
CS_B Setup/Hold
1.0
0.5
1.0
0.5
1.0
0.5
ns, Min
TSMCCW / TSMWCC
RDWR_B Setup/Hold
6.0
1.0
6.0
1.0
6.0
1.0
ns, Min
TSMCKBY
BUSY Propagation Delay
8.0
ns, Max
FCC_SELECTMAP
Maximum Frequency, master mode with
respect to nominal CCLK.
100
MHz, Max
FMAX_SELECTMAP
Maximum Configuration Frequency, slave
mode external CCLK
100
MHz, Max
FMAX_READBACK
Maximum Readback Frequency
80
MHz, Max
FMCCTOL
Frequency Tolerance, master mode with
respect to nominal CCLK.
±50
%
TSMCO
SelectMAP Readback Clock-to-Out
8.0
ns, Max
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